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IEEE 802.11 WLAN - HDL Optimized Beacon Frame Receiver with Captured Data

This example shows a hardware friendly model that receives beacon frames in an 802.11 wireless local area network (WLAN) as described in [ 1 ]. For more information refer to the IEEE 802.11 WLAN - Beacon Frame Receiver with Captured Data example.

Introduction

The IEEE 802.11 WLAN - Beacon Frame Receiver with Captured Data example shows the reception of beacon frames in an 802.11 based wireless local area network (WLAN). Three major modifications have been made to this example so that it generates efficient HDL code.

  • Streaming Input and Output: The HDL optimized beacon frame receiver processes data one sample at a time. The captured real-world signal is streamed into the receiver front-end. The streaming output of the receiver controller is buffered and passed to the detector, which operates on the data on a per-frame basis.

  • Fixed-point: The receiver front-end and the controller logic operate in fixed-point mode.

  • HDL optimized architecture: Several blocks have been redesigned to use hardware efficient algorithms and architectures.

The beacon frame example consists of three main components: front end, receiver controller, and detector. The front end and the receiver controller operate at a high rate in the receiver, so they have been optimized for HDL code generation in this example. The following sections describe the details of the modifications.

Receiver Front-End

The receiver front-end design is modeled in the subsystem HDLRx Front End. The receiver front-end is composed of a matched-filter, AGC, and coarse frequency compensation.

Modifications were made to the coarse frequency estimation algorithm [ 2 ] implemented in the original beacon receiver model:

  • The auto correlation operation has been replaced by a simple smooth filter.

  • The angle function has been implemented using the Complex to Magnitude-Angle HDL Optimized block. This block computes the phase using the hardware friendly CORDIC algorithm. To learn more about the Complex to Magnitude-Angle HDL Optimized block, refer to the DSP System Toolbox documentationdocumentation.

  • The detected phase offset is sent to NCO HDL Optimized block to generate a complex exponential signal that is used to correct the phase offset in the original signal.

The NCO HDL Optimized block provides hardware friendly options, maps the lookup table into a ROM, and provides a lookup table compression option to significantly reduce the lookup table size. To learn more about HDL support for HDL Optimized NCO block, refer to the documentationdocumentation.

Receiver Controller

The receiver controller finds the correlation between the phase offset corrected signal and synchronization signal. When the peak of the correlation is detected, the signal is delayed based on the peak position before despreading. Because of the large beacon frame size (2816 samples), implementing the correlator using either an FFT or a matched filter is not efficient in hardware. In addition, finding the maximum of a 2816-element vector is not hardware friendly. The correlation and despreading algorithm has been redesigned in this example. Despreading is performed before the correlation, aiming to reduce the filter size from 2816 to 128. Because the start of the beacon signal is unknown when performing the despreading early, 22 channels have been designed in the Despread_Matched Filter module, with each channel offsetting the adjacent channel by one sample. The maximum of the outputs of 22 filters is computed and the despread results from the channel that produces the maximum are selected to send to the Detector.

The downsample operation before the 22-channel matched filter in the Despread_Matched Filter subsystem shown below allows the possibility of sharing resources across the 22 channels of the FIR matched filters, as a way to balance the hardware speed and resource usage. To enable the sharing of resources, the ChannelSharing HDL property for the Discrete FIR Filter has been turned on. this reuses the FIR Filter hardware across all 22 channels. To see this property, right-click on the Discrete FIR Filter block, choose HDL Code, then HDL Block Properties. From the command line, you can use hdlget_param to get, hdlset_param to set and hdldispblkparams to display the HDL properties of a block.

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HDL Block Parameters ('commwlan80211BeaconRxhdl/HDLRx/HDLRx Controller/Despread_Matched Filter/Discrete FIR Filter')
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Implementation

	Architecture : Fully Parallel

Implementation Parameters

	AddPipelineRegisters : on
	ChannelSharing : on
	CoeffMultipliers : factored-csd

The despreaded signal is buffered in frames of 128 symbols before being processed in the detector. In the original Beacon Frame Receiver example, the PLCP information was fed back to the receiver controller to decide the length of payload to be collected. In this example, in order to simplify the interface between the hardware and software components and not require real-time communication of information between the two, the maximal length of the payload is collected in the hardware and sent to the software.

Results and Displays

When you run the simulation, it displays several scopes. The synchronization scope and the MPDU GUI are displayed in this section. You can refer to the IEEE 802.11 WLAN - Beacon Frame Receiver with Captured Data example for more information about the scopes.

HDL Code Generation

Pipeline registers (shown in green) have been added throughout the model to make sure the receiver front-end and the controller run at the expected speed. The HDL code generated from the receiver front-end and the controller were synthesized using Xilinx ISE on a Virtex6 (xc6vlx75t) FPGA, and the circuit ran at about 150 MHZ, which is sufficient to process the data in real time.

To check and generate HDL code of this example, you must have an HDL Coder™ license.

You can use the commands makehdl('commwlan80211BeaconRxhdl/HDLRx') and makehdltb('commwlan80211BeaconRxhdl/HDLRx') to generate HDL code and testbench for the fromt end and receiver controller.

Note: Test bench generation takes a long time due to the large amount of data in the simulation. You may want to reduce the simulation time before generating the test bench.

References

  1. IEEE Std 802.11-2007: IEEE Standard for Information technology - Telecommunications and information exchange between systems - Local and metropolitan area networks - Specific requirements, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, IEEE, New York, NY, USA, 1999-2007.

  2. M. Luise and R. Reggiannini, "Carrier frequency recovery in all-digital modems for burst-mode transmissions," IEEE Trans. Communications, pp. 1169-1178, Feb.-March-Apr. 1995.

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