Third-Party Products & Services


Comprehensive, integrated environment for digital IC design and verification


  • Mixed VHDL, Verilog, SystemC, SystemVerilog, and EDIF simulation
  • SLP accelerated simulation technology
  • C/C++ co-simulation and debugging
  • PLI and VHPI interface
  • Optimized timing simulation with SDF
  • Automated test bench generation


Active-HDL suite is a comprehensive, integrated environment for digital IC design and verification that employs hardware description languages and C/C++ solutions. Active-HDL suite has been designed based on customer suggestions and feedback to ensure design productivity and ease-of-use. Active-HDL supports complex FPGA and ASIC designs.

Aldec's HDL-based simulation environment for FPGA and ASIC designs has a built-in interface to the intuitive, technical computing MATLAB environment. This interface simplifies the verification of hardware design, provides robust visualization and analysis tools, allows extending HDL test benches by using MATLAB code to create complex stimuli, perform UUT data analysis, or visualize simulated data as clearly as possible. The Simulink interface in Active-HDL adds the ability to co-simulate mathematical and hardware components of system-level design and gives the flexibility of successive replacement of mathematical models describing the system with target HDL equivalents.

Aldec, Inc.

2260 Corporate Circle
Suite 480
Henderson, NV 89074
Tel: 702-990-4400
Tel: 800 487-8743

Required Products


  • Windows


  • E-mail
  • Fax
  • On-site assistance
  • System integration
  • Telephone
  • Training

Product Type

  • Data Analysis Tools
  • Modeling and Simulation Tools


  • Image Processing and Computer Vision
  • System Modeling and Simulation
  • Telecommunications


  • Aerospace and Defense
  • Communication Infrastructure
  • Consumer Electronics
  • Semiconductor