MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available. HDL Verifier enables design verification engineers developing FPGA and ASIC designs to generate UVM components and test benches directly from Simulink models and use them in simulators that support UVM such as those from Synopsys, Cadence, and Mentor.
A recent study by Wilson Research Group found that 48% of FPGA design projects and 71% percent of ASIC design projects rely on UVM for design verification. Typically, algorithm developers and system architects develop new algorithmic content in MATLAB and Simulink. Design verification (DV) engineers then use the MATLAB and Simulink models as a reference as they handwrite code for RTL test benches, which can be an extremely time-consuming process. Now with HDL Verifier, DV engineers can automatically generate UVM components such as sequences or scoreboards from system-level models already developed in Simulink. This approach reduces the time verification engineers spend developing test benches for ASIC and FPGA designs used in applications such as wireless communications, embedded vision, and controls.
“Simulink allows for us to reduce time spent on hand-writing production UVM test benches, test sequences and scoreboards by about 50% - leaving more time for us to focus on application for breakthrough innovations,” said Khalid Chishti, ASIC development manager, Allegro MicroSystems. “Our ASICs designed for automotive applications rely on UVM for production verification – MATLAB and Simulink simplify the once tedious task of developing the algorithms for these devices.”
With new features such as generation of UVM components, SystemVerilog assertions, and SystemVerilog DPI components from MATLAB and Simulink, HDL Verifier now offers extended support to design verification teams responsible for production verification of ASICs and FPGAs. Tasked with developing rigorous test benches in HDL simulators by handwriting code in SystemVerilog, these design verification teams can now generate verification components directly from existing MATLAB and Simulink models, and re-use these models to speed creation of production verification environments.
“According to the 2018 Functional Verification Study by Wilson Research and Mentor Graphics, DV engineers spend about one-fifth of their time on ASIC and FPGA projects in test bench development,” said Eric Cigan, principal HDL product marketing manager, MathWorks. “HDL Verifier’s capability to generate UVM and SystemVerilog DPI components from existing MATLAB and Simulink models can boost the productivity of DV engineers and improve collaboration between system architects, hardware designers, and DV engineers.”
HDL Verifier R2019b is available immediately worldwide.
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