bitror

Bitwise rotate right

Syntax

c = bitror(a, k)

Description

c = bitror(a, k) returns the value of the fixed-point fi object, a, rotated right by k bits. bitror rotates bits from the least significant bit (LSB) side into the most significant bit (MSB) side. It performs the rotate right operation on the stored integer bits of a.

bitror does not check overflow or underflow. It ignores fimath properties such as RoundingMode and OverflowAction.

a and c have the same fimath and numerictype properties.

Examples

Rotate Bits of a fi Object Right

Create an unsigned fixed-point fi object with a value 5, word length 4, and fraction length 0.

a = fi(5,0,4,0);
disp(bin(a))

0101

Rotate a right 1 bit.

disp(bin(bitror(a,1)))

1010

Rotate a right 2 bits.

disp(bin(bitror(a,2)))

0101

Rotate Bits in a Vector Right

Create a vector of fi objects.

a = fi([1,2,5,7],0,4,0);
disp(bin(a))

0001   0010   0101   0111

Rotate the bits in vector a right 1 bit.

disp(bin(bitror(a,fi(1))))

1000   0001   1010   1011

Rotate Bits Right Using fi to Specify Number of Bits to Rotate

Create an unsigned fixed-point fi object with a value 5, word length 4, and fraction length 0.

a = fi(5,0,4,0);
disp(bin(a))

0101

Rotate a right 1 bit where k is a fi object.

disp(bin(bitror(a,fi(1))))

1010

Input Arguments

a — Data that you want to rotate

scalar | vector | matrix | multidimensional array

Data that you want to rotate, specified as a scalar, vector, matrix, or multidimensional array of fi objects. a can be signed or unsigned.

Data Types: fixed-point fi

Complex Number Support: Yes

k — Number of bits to rotate

non-negative, integer-valued scalar

Number of bits to rotate, specified as a non-negative integer-valued scalar fi object or built-in numeric type. k can be greater than the word length of a. This value is always normalized to mod(a.WordLength,k).

Data Types: fi |single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using MATLAB® Coder™.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

For VHDL^®, generates the ror operator.

For Verilog^®, generates the following expression (where wl is the word length of a:

a >> idx || a << wl - idx

Version History

Introduced in R2007b