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Capture data to MATLAB or Simulink from RFSoC devices

Capture raw data using FPGA input and output (IO) application programming interface (API) from the Xilinx^® Zynq^® UltraScale+™ ZCU111 evaluation kit or Xilinx Zynq UltraScale+ ZCU216 evaluation kit. Configure an SoC model for the HDL code generation by using the HDL Workflow Advisor. Generate the HDL code for your algorithm, build and deploy the HDL design on an RFSoC device, and run a MATLAB^® script to interactively capture data from the deployed HDL design.

Topics

Create RFSoC HDL Coder Models
This workflow customizes and designs an RFSoC model using the Zynq RFSoC Template Builder tool.
ARM Targeting
Design and deploy algorithms to the ARM processor.

Tools

Zynq RFSoC Template Builder

Generate template model based on selected RFSoC reference design (Since R2021a)

Classes

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Board and Workflow

`hdlcoder.Board`	Board registration object that describes SoC custom board
`hdlcoder.WorkflowConfig`	Configure HDL code generation and deployment workflows
`hdlcoder.ReferenceDesign`	Reference design registration object that describes SoC reference design

Functions

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Export Reference Design

socExportReferenceDesign Export custom reference design for HDL Workflow Advisor (Since R2020a)

Add Interfaces

`addExternalIOInterface`	Define external IO interface for board object
`addExternalPortInterface`	Define external port interface for board object
`addInternalIOInterface`	Add and define internal IO interface between generated IP core and existing IP cores
`addAXI4MasterInterface`	Add and define AXI4 Master interface
`addAXI4SlaveInterface`	Add and define AXI4 slave interface
`addAXI4StreamInterface`	Add AXI4-Stream interface (Since R2020a)
`addAXI4StreamVideoInterface`	Add AXI4-Stream Video interface (Since R2020a)
`addClockInterface`	Add clock and reset interface

Board and Reference Design

`addCustomVivadoDesign`	Specify Xilinx Vivado exported block design Tcl file
`addIPRepository`	Include IP modules from your IP repository folder in your custom reference design
`addParameter`	Add and define custom parameters for your reference design
`validateReferenceDesign`	Check property values in reference design object
`validateBoard`	Check property values in board object

Callback Functions

`CallbackCustomProgrammingMethod`	Function handle for custom callback function that gets executed during Program Target Device task in the Workflow Advisor
`EmbeddedCoderSupportPackage`	Specify whether to use an Embedded Coder support package
`PostBuildBitstreamFcn`	Function handle for callback function that gets executed after Build FPGA Bitstream task in the HDL Workflow Advisor
`PostCreateProjectFcn`	Function handle for callback function that gets executed after Create Project task in the HDL Workflow Advisor
`PostSWInterfaceFcn`	Function handle for custom callback function that gets executed after Generate Software Interface task in the HDL Workflow Advisor
`PostTargetInterfaceFcn`	Function handle for callback function that gets executed after Set Target Interface task in the HDL Workflow Advisor
`PostTargetReferenceDesignFcn`	Function handle for callback function that gets executed after Set Target Reference Design task in the HDL Workflow Advisor

Featured Examples

DAC and ADC Loopback Data Capture

Capture raw analog-to-digital converter (ADC) data using the FPGA I/O API from the Xilinx® Zynq® UltraScale+™; ZCU111 evaluation kit or Xilinx Zynq UltraScale+ ZCU216 evaluation kit. This example uses the HDL Workflow Advisor to configure an SoC model for HDL code generation. In this example, you generate the HDL code for your algorithm, build and deploy the HDL design on an RFSoC device, and run a MATLAB® script to interactively capture data from the deployed HDL design.

Open Script

IQ Mixer Mode Capture

Enable the RFSoC built-in numerically-controlled oscillator (NCO) mixer. The mixer design uses a different data format that, instead of providing real signals, provides a complex in-phase and quadrature (IQ) signal to a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC). There is more data to transfer to direct memory access (DMA) and back to MATLAB® given that you need to transfer I and Q samples back. You can accommodate this larger data width by increasing the DMA data width to 128 bits.

Open Script