Input data type

HDL data type for the input ports of the model

Model Configuration Pane: Global Settings / Ports

Description

Specify the HDL data type for the input ports of the model.

Dependencies

This option is enabled when the target language (specified by the Language option) is VHDL^®.

Settings

std_logic_vector (default) | signed/unsigned

For VHDL, the options are:

Default: std_logic_vector

std_logic_vector

Specifies VHDL type STD_LOGIC_VECTOR.

signed/unsigned

Specifies VHDL type SIGNED or UNSIGNED.

For Verilog^® and SystemVerilog, the options are:

Default: wire

In generated Verilog and SystemVerilog code, the data type for all ports is 'wire', and cannot be modified. Therefore, Input data type is disabled when the target language is Verilog or SystemVerilog.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

Recommended Settings

No recommended settings.

Programmatic Use

Parameter: InputType

Type: character vector

Value: (for VHDL)'std_logic_vector' | 'signed/unsigned', (for Verilog) 'wire'

Default: (for VHDL), 'std_logic_vector' (for Verilog) 'wire'

Version History

Introduced in R2012a