Scalarize ports

Vector ports flattened into scalar ports

Model Configuration Pane: Global Settings / Ports

Description

Flatten vector ports into a structure of scalar ports in VHDL^® code.

Dependencies

When the target language (specified by the Language option) is VHDL, this option is enabled.

Settings

off (default) | on | DUT Level

Default: Off

on

When generating code for a vector port, generate a structure of scalar ports.

off

When generating code for a vector port, generate a type definition and port declaration for the vector port.

DUT Level

When generating code for a vector port, generate a structure of scalar ports for vector ports that are at only DUT level. The DUT subsystem does not have to be at the top level of your model.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

Recommended Settings

No recommended settings.

Programmatic Use

Parameter: ScalarizePorts

Type: character vector

Value: 'on' | 'off' | 'DUT Level'

Default: 'off'

Version History

Introduced in R2012b