VHDL architecture name

Architecture name for DUT

Model Configuration Pane: Global Settings / General

Description

Specify the architecture name for your DUT in the generated HDL code.

'rtl' (default) | character vector

Default: 'rtl'

Specify the VHDL^® architecture name for your DUT in the generated HDL code as a character vector.

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example:

Pass the property as an argument to the makehdl function.
```
makehdl(gcb,'VHDLArchitectureName','_rtl2')
```
When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.
```
hdlset_param(gcs,'VHDLArchitectureName','_rtl2')
makehdl('myDUT')
```

No recommended settings.

Parameter: VHDLArchitectureName

Type: character vector

Default: 'rtl'

Introduced in R2012a