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Minimize Clock Enables and Reset Signal Parameters

This page describes parameters that reside in the HDL Code Generation > Global Settings > Ports tab of the Configuration Parameters dialog box.

Minimize clock enables

Omit generation of clock enable logic for single-rate designs.

Settings

Default: Off

On

For single-rate models, omit generation of clock enable logic wherever possible. The following VHDL® code example does not define or examine a clock enable signal. When the clock signal (clk) goes high, the current signal value is output.

Unit_Delay_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      Unit_Delay_out1 <= to_signed(0, 32);
    ELSIF clk'EVENT AND clk = '1' THEN
      Unit_Delay_out1 <= In1_signed;
    END IF;
  END PROCESS Unit_Delay_process;
Off

Generate clock enable logic. The following VHDL code extract represents a register with a clock enable (enb)

Unit_Delay_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      Unit_Delay_out1 <= to_signed(0, 32);
    ELSIF clk'EVENT AND clk = '1' THEN
      IF enb = '1' THEN
        Unit_Delay_out1 <= In1_signed;
      END IF;
    END IF;
  END PROCESS Unit_Delay_process;

Exceptions

In some cases, HDL Coder™ emits clock enables even when Minimize clock enables is selected. These cases are:

  • Registers inside Enabled, State-Enabled, and Triggered subsystems.

  • Multirate models.

  • The coder always emits clock enables for the following blocks:

    • commseqgen2/PN Sequence Generator

    • dspsigops/NCO

      Note

      HDL support for the NCO block will be removed in a future release. Use the NCO HDL Optimized block instead.

    • dspsrcs4/Sine Wave

    • hdldemolib/HDL FFT

    • built-in/DiscreteFir

    • dspmlti4/CIC Decimation

    • dspmlti4/CIC Interpolation

    • dspmlti4/FIR Decimation

    • dspmlti4/FIR Interpolation

    • dspadpt3/LMS Filter

    • dsparch4/Biquad Filter

Note

If your design uses a RAM block such as a Dual Rate Dual Port RAM with the RAM Architecture set to Generic RAM without Clock Enable, the code generator ignores the Minimize clock enables setting.

Command-Line Information

Property: MinimizeClockEnables
Type: character vector
Value: 'on' | 'off'
Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, to minimize Clock Enable signals when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model, use either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
            'MinimizeClockEnables','on')
  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.

    hdlset_param('sfir_fixed','MinimizeClockEnables','on')
    makehdl('sfir_fixed/symmetric_fir')

Minimize global resets

Omit generation of reset logic in the HDL code.

Settings

Default: Off

On

When you enable this setting, the code generator tries to minimize or remove the global reset logic from the HDL code. This code snippet corresponds to the Verilog code generated for a Delay block in the Simulink® model. The code snippet shows that HDL Coder removed the reset logic.

 always @(posedge clk)
    begin : Delay_Synchronous_process
      if (enb) begin
        Delay_Synchronous_out1 <= DataIn;
      end
    end
Off

When you disable this parameter, HDL Coder generates the global reset logic in the HDL code. This Verilog code snippet shows the reset logic generated for the Delay block.

  always @(posedge clk or posedge reset)
    begin : Delay_Synchronous_process
      if (reset == 1'b1) begin
        Delay_Synchronous_out1 <= 1'b0;
      end
      else begin
        if (enb) begin
          Delay_Synchronous_out1 <= DataIn;
        end
      end
    end

Dependency

If you select Minimize global resets, the generated HDL code contains registers that do not have a reset port. If you do not initialize these registers, there can be potential numerical mismatches in the HDL simulation results. To avoid simulation mismatches, you can initialize the registers by using the No-reset registers initialization setting.

By default, the No-reset registers initialization setting has the value Generate initialization inside module, which means that the code generator initializes the registers as part of the HDL code generated for the DUT. To initialize the registers with the script, set No-reset registers initialization to Generate an external script. You must use a zero initial value for the blocks in your Simulink model.

Exceptions

Sometimes, when you select Minimize global resets, HDL Coder generates the reset logic, if you have:

  • Blocks with state that have a nonzero initial value, such as a Delay block with non-zero Initial Condition.

  • Enumerated data types for blocks with state.

  • Subsystem blocks with BlackBox HDL architecture where you request a reset signal.

  • Multirate models with Timing controller architecture set to default.

    If you set Timing controller architecture to resettable, HDL Coder generates a reset port for the timing controller. If you set Minimize global reset signals to 'on', the code generator removes this reset port.

  • Truth Table

  • Chart

  • MATLAB Function block

Command-Line Information

Property: MinimizeGlobalResets
Type: character vector
Value: 'on' | 'off'
Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, to minimize global reset signals when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model, use either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
            'MinimizeGlobalResets','on')
  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.

    hdlset_param('sfir_fixed','MinimizeGlobalResets','on')
    makehdl('sfir_fixed/symmetric_fir')