FPGA-in-the-Loop Simulation

Verification with FPGA hardware

Run a Simulink^® or MATLAB^® simulation that is synchronized with an HDL design running on an Intel^® FPGA board.

Topics

FPGA-in-the-Loop Simulation
FPGA-in-the-loop (FIL) simulation provides the capability to use Simulink or MATLAB software for testing designs in real hardware for any existing HDL code.
FPGA-in-the-Loop Simulation Workflows
Choose between generating a block or System object™, and decide whether to use the FIL Wizard or HDL Workflow Advisor.

Related Information

FPGA Debug

Featured Examples

Verify HDL Implementation of PID Controller Using FPGA-in-the-Loop

Verify HDL Implementation of PID Controller Using FPGA-in-the-Loop

Set up an FPGA-in-the-Loop (FIL) application using HDL Verifier™.

Open Script