This example shows how to model a Reset-dominant SR-Latch from Simscape™ Electrical™ logic components. Initial conditions are passed to the relevant AND gates via the initialization commands of the switches.
The plots below show the inputs and outputs for the Reset-Dominant SR-Latch. Both inputs to the SR-Latch are set high, and Q follows the opposite to the pulse signal. Output Q changes everytime the pulse is modified. The output ~Q stays low.