Ground unconnected input port
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The Ground block connects to blocks whose input ports do not connect to other blocks. If you run a simulation with blocks that have unconnected input ports, Simulink® issues warnings. Using a Ground block to ground those unconnected blocks can prevent these warnings.
Working with Fixed-Point Data Types
When working with fixed-point data types, there may be instances where the fixed-point data type cannot represent zero exactly. In these cases, the Ground block outputs a nonzero value that is the closest possible value to zero. This behavior applies only to fixed-point data types with nonzero bias. These expressions are examples of fixed-point data types that cannot represent zero:
fixdt(0, 8, 1, 1)— an unsigned 8-bit type with slope of 1 and bias of 1
fixdt(1, 8, 6, 3)— a signed 8-bit type with slope of 6 and bias of 3
Working with Enumerated Data Types
When working with enumerated data types, the Ground block outputs the default value of the enumeration. This behavior applies whether:
The enumeration can represent zero
The default value of the enumeration is zero
If the enumerated type does not have a default value, the Ground block outputs the first enumeration value in the type definition.
Port_1 — Ground signal
The Ground block outputs a scalar signal with zero value, and the same data type as the port to which it connects.
fixed point |
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has a single, default HDL architecture.
Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
This block supports code generation for complex signals.