Detect Specified Minimum and Maximum Value Violations

Check ID: mathworks.sldv.minmax

Detect signals which exceed specified minimum and maximum values

Description

This analysis checks the specified minimum and maximum values (the design ranges) on intermediate signals throughout the model and on the output ports. If the analysis detects that a signal exceeds the design range, the results identify where in the model the errors occurred.

Following the recommendations of this check increases the likelihood of generating MISRA C:2012 compliant code for embedded applications, as well as code that complies with the CERT C and CWE standards.

Results and Recommended Actions

Result	Recommended Action
Failed, model incompatible	Resolve the model incompatibility. See Supported and Unsupported Simulink Blocks in Simulink Design Verifier (Simulink Design Verifier) Support Limitations for Model Blocks (Simulink Design Verifier) Support Limitations for Simulink Software Features (Simulink Design Verifier) Support Limitations for Stateflow Software Features (Simulink Design Verifier) Support Limitations for MATLAB for Code Generation (Simulink Design Verifier) Also see Handle Incompatibilities with Automatic Stubbing (Simulink Design Verifier).
Violation of minimum and/or maximum found in model	To view the conditions that cause the violation, create a harness model. When you simulate the harness, the inputs replicate the error. Click View test case in the Model Advisor report.

See Also

• MISRA C:2012: Directive 4.1

• CERT C, API00-C

• CWE, CWE-628

• Secure Coding (Embedded Coder)

• Detect and Address Run-Time Errors (Simulink Design Verifier)

• Check for Specified Minimum and Maximum Value Violations (Simulink Design Verifier)