Configure IP Core for Software Interface
R2026bCreate a software interface model that includes the algorithm to run on the embedded processor of the target platform. The input is your tested and verified IP core model. The software interface model interacts with the deployed IP core on the FPGA and implements communication between the FPGA and the processor. You can then generate and deploy code from the model to run the algorithm on the embedded processor on your SoC device or Simulink® Real-Time™ target machine.
For more details about the workflow, see Targeting FPGA and SoC Hardware Overview (HDL Coder).
Topics
- Choose a Method to Interact with IP Cores on Target Hardware (HDL Coder)
Choose a software interface method to interact with IP cores running on target hardware.
- Generate Software Interface Model to Probe and Rapidly Prototype HDL IP Core (HDL Coder)
Generate software interface model to communicate with the HDL IP core and perform rapid prototyping.
- Generate Device Tree for IP Core (HDL Coder)
Generate device tree files that include the HDL Coder™ generated IP core.
