Bandwidth derating (%)

Model memory transaction inefficiencies

Model Configuration Pane: Target hardware resources / FPGA design (PS mem controllers)

Description

Model memory transaction inefficiencies specified by a derating percentage value. For every 100 clocks, memory transaction execution is paused for the number of clocks equal to Bandwidth derating. To set this parameter, measure the maximum bandwidth on your board and reflect the bandwidth derating from your board in this parameter. See an example in Analyze Memory Bandwidth Using Traffic Generators.

Settings

2.3 (default)

Default: 2.3

Programmatic Use

Parameter:

Type:

Values: 2.3

Default: 2.3

Version History

Introduced in R2019a