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Program Standalone Altera FPGA Development Board from Simulink

This example shows how to target an Altera® FPGA development board for synthesis using the FPGA Turnkey workflow.

The hdlcoderUARTServoControllerExampleAltera model is designed to work with an Altera DE2-115 development and education board. The UART_Servo_on_FPGA subsystem receives commands through UART ports. The subsystem generates a pulse width modulation (PWM) waveform to control a servo motor.

Before You Begin

To run this example, you must have your synthesis tool set up. To learn how to set up your synthesis tool, see Synthesis Tool Path Setup.

This example uses the Altera DE2-115 development and education board. You can try this example with a different board, and specify the target interface according to that board’s interface definition. To see a list of Altera boards supported for the FPGA Turnkey workflow, see Supported EDA Tools and Hardware.

If you want to download the programming file, you must first connect the target device. However, if the target device is not connected, you can still generate the programming file.

Open the Model

  1. Add the example directory to your MATLAB® path.

  2. Open the model.


Select the Target Device

  1. Right-click the UART_Servo_on_FPGA subsystem and select HDL Code > HDL Workflow Advisor.

  2. In the HDL Workflow Advisor, select the Set Target > Set Target Device and Synthesis Tool task.

  3. For Target workflow, select FPGA Turnkey.

  4. For Target platform, select Altera DE2-115 development and education board.

    If the board does not automatically appear in the list, select Get more boards to download the Altera FPGA Boards support package.

    The HDL Workflow Advisor automatically sets the synthesis tool based on your board selection.

  5. Click Run This Task .

Set Target Interface and Target Frequency

  1. In the left pane of the HDL Workflow Advisor, select the Set Target Interface task.

  2. For each port, select an option from the Target Platform Interfaces menu as shown in the following figure, and click Apply.

    Each port is allocated to a specified bit position [b] or range of bit positions [lsb:msb]. The width of the specification, in bits, must equal the width of the port on the DUT. When you select options, the HDL Workflow Advisor automatically allocates a bit range. You can double-click in the Bit Range / Address / FPGA Pin column to edit the value.

    For detailed information on each Target Platform Interfaces option, refer to your board documentation.


    You must allocate at least one output port must to the target device. If you do not allocate any ports, the Set Target Interface task displays an error and terminates.

  3. Click Run This Task.

  4. In the Set Target Frequency task, set FPGA system clock frequency to 100 MHz, then click Run This Task.

    In this example, the target frequency must be 100 MHz due to the fixed UART baud rate.

Generate Code, Synthesize, and Program Target Device

After selecting the target device and configuring its port interface, the HDL Workflow Advisor can perform the next sequence of tasks automatically. These tasks include:

  • Prepare Model For HDL Code Generation: Checking the model for HDL code generation compatibility.

  • HDL Code Generation: Setting HDL-related options of the Model Configuration Parameters dialog box and generating HDL code.

  • FPGA Synthesis and Analysis: Executing synthesis and timing analysis in Altera Quartus II. Back-annotating the model with critical path information obtained during synthesis.

  • Download to Target has two subtasks:

    • Generate Programming File: Generating an FPGA programming file.

    • Program Target Device: Downloading the programming file to the board.

To run this sequence of tasks automatically:

  1. Open the Download to Target task group.

  2. Right-click Program Target device and select Run to Selected Task.

    The task sequence concludes by programming your target board with the generated programming file. You can then read the code generation and synthesis log files.