HDL Verifier™ Support Package for Microsemi^® FPGA Boards contains the board definition files for FPGA-in-the-loop (FIL) simulation with HDL Verifier and supported Microsemi FPGA and SoC FPGA boards. With FIL simulation, use MATLAB^® or Simulink^® to test designs in real hardware for any existing HDL code. The HDL code can either be manually written or generated from a model subsystem.