HDL Verifier Support Package for Microchip FPGA Boards

Debug and test HDL code on Microchip FPGAs using FPGA-in-the-loop

Release Notes
PDF Documentation

Release Notes
PDF Documentation

HDL Verifier™ Support Package for Microchip FPGA Boards contains the board definition files for FPGA-in-the-loop (FIL) simulation with HDL Verifier and supported Microchip FPGA and SoC FPGA boards. With FIL simulation, use MATLAB^® or Simulink^® to test designs in real hardware for any existing HDL code. The HDL code can either be manually written or generated from a model subsystem.

Setup and Configuration

Install hardware support, update firmware, configure hardware connection

FPGA-in-the-Loop Simulation

Verification with FPGA hardware