Access on-board memory locations from MATLAB or Simulink by using the MATLAB AXI master IP in your FPGA design. This IP connects to slave memory locations on the board. The IP also responds to read and write commands from MATLAB or Simulink, over JTAG, PCI Express, or Ethernet cable.
|Add AXI master IP path to Vivado project|
|Read data out of AXI4 memory-mapped slaves|
|Write data to AXI4 memory-mapped slaves|
|Release JTAG or Ethernet cable resource|
|Copy board-specific SD card image files to host SD card location|
|Load board-specific SD card image files to target SoC device SD card location|
|Load custom FPGA bitstream and its corresponding DTB file to target SoC device|
|Read and write memory locations on FPGA board from MATLAB|
High-level steps for accessing memory-mapped locations on an FPGA board from MATLAB or Simulink.
Integrate and configure Ethernet MATLAB AXI master.
Configure Ethernet MATLAB AXI master for Xilinx Zynq SoC devices.
Integrate and configure MATLAB as AXI Master IP over PCI Express.
Access memory-mapped locations on an FPGA board from Simulink.
Simulate MATLAB AXI master using the Vivado simulator.