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Ethernet MATLAB AXI Master

Integrate and configure MATLAB® AXI master over Ethernet using user datagram protocol (UDP). To use Ethernet MATLAB AXI master, you must first include these two intellectual property (IP) blocks in your project: Ethernet media access controller (MAC) Hub and UDP MATLAB as AXI Master.

Ethernet MAC Hub IP

The Ethernet MAC Hub IP connects the Ethernet physical layer (PHY) to the UDP MATLAB as AXI Master IP. Use the following Ethernet MAC Hub IPs to connect the target FPGA board through various types of interfaces.

  • Ethernet MAC Hub GMII IP — This IP supports the gigabit media independent interface (GMII).

  • Ethernet MAC Hub MII IP — This IP supports the media independent interface (MII).

  • Ethernet MAC Hub GMII IP and 1G/2.5G Ethernet PCS/PMA or SGMII Xilinx® IP — Connect these two IPs to support the serial gigabit media independent interface (SGMII).

Interface of Ethernet MAC Hub IP

Interface of Ethernet MAC Hub IP

The following tables provide the port description of Ethernet MAC Hub GMII and Ethernet MAC Hub MII.

PortDescription
s0_axisAXI-stream slave interface. Connect this port to the m_axis port on the UDP MATLAB as AXI Master IP.
m0_axisAXI-stream master interface. Connect this port to the s_axis port on the UDP MATLAB as AXI Master IP.

Ethernet MAC Hub GMII IP Ports

PortDirectionDescription
ref_clkInputReference clock signal that drives phy_gtxclk. The frequency of ref_clk must be the same as the phy_rxclk clock frequency.
ref_resetInputIP reset signal.
phy_rxclkInputReceive clock from PHY.
phy_rxd[7:0]InputReceive data signal from PHY.
phy_rxdvInputReceive data valid control signal from PHY.
phy_rxerInputReceive error signal from PHY.
rxclk_enInputReceiver clock enable.
txclk_enInputTransmitter clock enable.
phy_colInputCollision detect signal from PHY.
phy_crsInputCarrier sense detect signal from PHY.
axis_aclkInputClock signal for AXI-stream interface.
phy_gtxclkOutputClock to PHY.
phy_txd[7:0]OutputTransmit data signal to PHY.
phy_txenOutputTransmit enable control signal to PHY.
phy_txerOutputTransmit error signal to PHY.
axis_aresetnOutputActive-low reset. Reset signal for AXI-stream interface. You can use this port to reset the downstream AXI peripherals.

Ethernet MAC Hub MII IP Ports

PortDirectionDescription
axis_aclkInputClock signal for AXI-stream interface.
resetInputIP reset signal.
mii_colInputCollision detect signal from PHY.
mii_crsInputCarrier sense detect signal from PHY.
mii_rxclkInputReceive clock signal from PHY.
mii_rxd[3:0]InputReceive data signal from PHY.
mii_rxdvInputReceive data valid control signal from PHY.
mii_rxerInputReceive error signal from PHY.
mii_txclkInputTransmit clock signal from PHY.
axis_aresetnOutputActive-low reset. Reset signal for AXI-stream interface. You can use this port to reset the downstream AXI peripherals.
mii_txd[3:0]OutputTransmit data signal to PHY.
mii_txenOutputTransmit enable control signal to PHY.
mii_txerOutputTransmit error signal to PHY.
phy_mdcOutputManagement data clock (MDC) signal to PHY.
phy_mdioInoutData signal for communication with management data input/output (MDIO) controller.
phy_reset_nOutputActive-low reset signal to PHY.

For more information about port connections, see Access FPGA Memory Using Ethernet-Based MATLAB AXI Master.

Ethernet MAC Hub IP Connections for SGMII

For an SGMII, connect the Ethernet MAC Hub GMII IP to the 1G/2.5G Ethernet PCS/PMA or SGMII Xilinx IP as this figure shows.

Ethernet MAC Hub IP connections for SGMII

Ethernet MAC Hub IP Parameters

Based on the type of Ethernet interface of your target FPGA board, instantiate the Ethernet MAC Hub GMII or Ethernet MAC Hub MII HDL IP in your design. After instantiating the Ethernet MAC Hub IP in your design, open the block parameters for configuration. This figure shows the block parameters for the Ethernet MAC Hub GMII IP.

Ethernet MAC Hub IP parameters

Configure these parameters:

  • Number of AXI Stream Channels — This parameter decides the number of AXI-stream channels in the Ethernet MAC Hub IP. Select this value as an integer from 1 to 8. The default value is 1.

  • IP Address Byte1, IP Address Byte2, IP Address Byte3, IP Address Byte4 — These parameters set the four bytes in the range from 0 to 255 composing the UDP internet protocol (IP) address of the device. This address must match the DeviceAddress property value of the aximaster object.

  • UDP Port For Channel 1, UDP Port For Channel 2, UDP Port For Channel 3, UDP Port For Channel 4, UDP Port For Channel 5, UDP Port For Channel 6, UDP Port For Channel 7, UDP Port For Channel 8 — These parameters set the UDP port numbers. Specify each parameter value as an integer from 255 to 65,535. These port numbers must match the Port property value of the aximaster object.

Ethernet MAC Hub IP Limitations

  • For SGMII, the clock signal for the AXI-Stream interface (axis_aclk) is limited to 50 MHz.

  • Ethernet management interfaces MDC and MDIO do not enable you to configure the Ethernet PHY.

UDP MATLAB as AXI Master IP

The UDP MATLAB as AXI Master HDL IP connects the Ethernet MAC Hub IP to your application IP. The UDP MATLAB as AXI Master IP acts as a bridge that translates data between an AXI peripheral and MATLAB.

Interface of UDP MATLAB as AXI Master IP

Interface of UDP MATLAB as AXI Master IP

The interface of the UDP MATLAB as AXI Master IP includes the ports described in these tables.

PortDescription
s_axisAXI-stream slave interface.
m_axisAXI-stream master interface.
axi4mAXI4-full master interface.

UDP MATLAB as AXI Master IP Ports

PortDirectionDescription
axis_aclkInputClock signal for AXI-stream interface.
axis_aresetnInputActive-low reset signal for AXI-stream interface.
aclkInputClock signal for AXI4-full interface.
aresetnInputActive-low reset. Reset signal for AXI4-full interface.

UDP MATLAB as AXI Master IP Parameters

After instantiating the UDP MATLAB as AXI Master IP in your design, open the block parameters for configuration.

UDP MATLAB as AXI Master IP parameters

Configure these parameters:

  • AXI Address Width — This parameter is the address bus width in bits. The IP supports 32 bits or 64 bits.

  • AXI Data Width — This parameter is the data bus width in bits. The IP supports 32 bits or 64 bits.

  • ID Width — This parameter is the ID width in bits. Its value must match the ID width of the AXI4 slave.

When the program is running on your FPGA board, you can create a MATLAB AXI master object using the aximaster object. To access the slave memory locations on the board, use the readmemory and writememory object functions.

See Also

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