HDL Coder™ can generate an IP core that you can deploy to the Xilinx FPGA boards. You can integrate the generated IP core into the default system reference design or into your own custom reference design that you can register for the board.
System for defining and registering boards and reference designs.
Define the interface and attributes of a custom SoC board. After defining the board, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.
Define the interface and attributes of a custom SoC reference design. After defining and registering the reference design, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.
Learn how to define custom parameters and custom callback functions for your custom reference design.
Learn how you can create an IP repository and add the IP modules in the repository to your custom reference design.