Program Standalone Xilinx FPGA Development Board from MATLAB
This example shows how to program a standalone FPGA with your MATLAB® design, using the FPGA Turnkey workflow.
The target device in this example is a Xilinx® Virtex-5 ML506 development board, but you can use this workflow with other Xilinx FPGAs. For a list of supported devices, see FPGA Turnkey Hardware.
Before You Begin
To use the FPGA Turnkey workflow, you must:
Have your synthesis tool path set up. To learn how to setup your synthesis tool path, see Synthesis Tool Path Setup.
Connect the target device if you want to program it immediately. If the target device is not connected, you can still generate the programming file.
Create a Project
Create a new folder to hold your project files.
At the MATLAB command line, open the design and test bench files:
edit mlhdlc_turnkey_led_blinking.m edit mlhdlc_turnkey_led_blinking_tb.m
Save copies of the design and test bench files to your new project folder.
Change directory to your new project folder.
At the MATLAB command line, enter:The project creation pane opens.
For Name, enter
myproject.prjand click OK.
Under MATLAB Function, click Add MATLAB Function and select
Under MATLAB Test Bench, click Add files and select
Click the Workflow Advisor button to open the HDL Workflow Advisor.
Convert Design To Fixed-Point
Right-click the Define Input Types task and select Run This Task.
In the Variables tab, for the
freqCountervariable, in the Proposed Type column, enter
numerictype(0, 27, 0)to set the type to unsigned 27-bit integer.
On the left, right-click the Fixed-Point Conversion task and select Run This Task.
Map Design Ports to Target Interface
In the Select Code Generation Target task, select the FPGA Turnkey workflow and Xilinx Virtex-5 ML506 development board as follows:
For Workflow, select FPGA Turnkey.
For Platform, select Xilinx Virtex-5 ML506 development board. If your target device is not in the list, select Get more to download the support package.
The coder automatically sets Chip family, Device, Package, and Speed according to your platform selection.
For FPGA clock frequency, for both Input and System, enter 100.
In the Set Target Interface task, map the design input and output ports to interfaces on the target device by setting the fields in the Target Platform Interfaces column as follows:
Blink_frequency_1to User Push Buttons N-E-S-W-C [0:4]
Blink_directionto User Push Buttons N-E-S-W-C [0:4]
LEDto LEDs General Purpose [0:7]
You can leave the
The HDL Workflow Advisor applies your settings immediately.
Generate Programming File and Download To Hardware
You can generate code, perform synthesis and analysis, and download the design to the target hardware using the default settings:
For the Synthesis and Analysis task group, uncheck the Skip this Step option.
For the Download to Target task group, uncheck the Skip this Step option.
Right-click Download to Target > Generate Programming File and select Run to Selected Task.
If your target hardware is connected and ready to program, select the Program Target Device subtask and click Run.