Use this support package with:
Xilinx® Vivado® 2020.1
Xilinx ISE 14.7
For tool setup instructions, see
HDL Coder™ can generate code from your algorithm in Simulink® or MATLAB® and deploy it to standalone FPGA boards. Use:
IP Core Generation to generate an HDL IP core for
your algorithm in MATLAB or Simulink, and then integrate the IP core into the default system
reference design or your own custom reference design that you register
for the board. This workflow supports Xilinx
Kintex®-7 series and the newer FPGA families.
FPGA Turnkey to generate HDL code for your
algorithm in Simulink or MATLAB, and the FPGA top level wrapper HDL code for running your
design on a standalone FPGA board. This workflow supports Xilinx ISE-based FPGA boards. For FPGA development boards that
have more than one FPGA device, only one such device can be used with
To use these workflows, you must have a supported FPGA board connected to your MATLAB host computer using a supported connection type, and a supported synthesis tool.
|Device Family||Board||IP Core Generation||FPGA Turnkey|
|Spartan®-3A DSP||Spartan-3A DSP 1800A development board||X|
|Spartan-6||Spartan-6 SP605 development board||X|
|Virtex-5 ML506 development board||X|
|Virtex-6 ML605 development board||X|
|Kintex-7 KC705 development board||X|
When you use the
IP Core Generation workflow, you can add
support for custom boards. For more information, see Board and Reference Design Registration System.
The board and reference design plugins that are used in theserves as an example when you add support for your own custom board.