Hardware I/O Devices

Model the connection between the IO devices on your board and your FPGA logic

Use these blocks to create models that simulate the connection between your SoC design and these IO devices.

Blocks

HDMI Rx	Convert video stream to YCbCr 4:2:2 pixel stream
HDMI Tx	Convert YCbCr 4:2:2 pixel stream to video frame
AD9361 Rx	Connect hardware logic to AD9361-based Zynq receiver
AD9361 Tx	Connect hardware logic to AD9361-based Zynq transmitter
Zynq and FMCOMMS2/3/4 Receiver Configuration	Connect hardware logic to FMCOMMS Zynq radio receiver hardware
Zynq and FMCOMMS2/3/4 Transmitter Configuration	Connect hardware logic to FMCOMMS Zynq radio transmitter hardware
ADAU1761 Codec	Connect hardware logic to ADAU1761 signals on hardware board
RF Data Converter	Provide RF data path interface to hardware logic
ADC To Vector	Convert concatenated 16-bit ADC input samples to vector outputs
Vector To DAC	Convert vector inputs to concatenated 16-bit DAC output samples
RFDC Bus Creator	Convert control signals into RF Data Converter real-time interface-compatible bus
RFDC Bus Selector	Convert RF Data Converter real-time interface-compatible bus into control signals
OTAVA DTRX2	Integrate OTAVA DTRX2 mmWave radio card with ZCU208 board
Aurora 64B66B	Provide high-speed serial communication using Xilinx Aurora interface

Featured Examples

Transmit and Receive Tone Using Xilinx RFSoC Device - Part 1 System Design

Design a data path for a Xilinx® RFSoC device by using SoC Blockset®. You will design and simulate a system that generates a sinusoidal tone from an FPGA and transmit the tone across multiple RF channels by using the RF Data Converter (RFDC) block. The system will then receive the data back into the FPGA by using the RFDC block and visualizes the received tone for one channel at a time by using an embedded processor.

Open Example

Transmit and Receive Tone Using Xilinx RFSoC Device - Part 2 Deployment

Implement and verify a design on Xilinx® RFSoC device using SoC Blockset™. You deploy a system on Xilinx RFSoC evaluation kits that generates a sinusoidal tone from an FPGA, transmits it across multiple RF channels, and receives it back into the device to complete the loopback. For modeling and simulation of the system, see the Transmit and Receive Tone Using Xilinx RFSoC Device - Part 1 System Design example.

Open Example

5G NR MIB Recovery Using Xilinx RFSoC Device

Simulate and deploy a 5G NR MIB Recovery algorithm in Simulink® using an SoC Blockset™ implementation targeted on the Xilinx® Zynq® UltraScale+™ RFSoC ZCU111 evaluation board. Using this example, you can recover, demodulate a primary synchronization signal (PSS) and secondary synchronization signal (SSS) and decodes MIB report from the 5G NR waveforms and simulate the Cell Search control algorithm sequence running on a processor while interacting with the Cell Search hardware algorithm. In simulation, you can fine tune and verify the controller in the processor and hardware algorithm in the FPGA at a system level before implementing them on the hardware.

Open Example

OFDM Transmit and Receive Using Xilinx RFSoC Device

Simulate and deploy an orthogonal frequency division multiplexing (OFDM) transmit and receive algorithm in Simulink® using an SoC Blockset™ implementation targeted on a Xilinx® Zynq® UltraScale+™ RFSoC ZCU111 evaluation board. Using this example, you can integrate HDL OFDM Transmitter (Wireless HDL Toolbox) and HDL OFDM Receiver (Wireless HDL Toolbox) examples into the SoC Blockset implementation.

Open Example

Vertical Video Flipping Using External Memory

Design an application to flip an incoming video stream vertically.

Contrast Limited Adaptive Histogram Equalization with External Memory

Implement the contrast-limited adaptive histogram equalization (CLAHE) algorithm for FPGA, including an external memory interface.

Pulse-Doppler Radar Using Xilinx RFSoC Device

Build, simulate, and deploy a pulse-Doppler radar system in Simulink® using an SoC Blockset™ implementation targeted on the Xilinx® Zynq® UltraScale+™ RFSoC evaluation kit. Using this example, you can detect and estimate the range and velocity of moving targets. The range-Doppler processing is partitioned across a field-programmable gate array (FPGA) and a processor. The range processing is handled in the FPGA and the Doppler processing is handled in the processor. The example also implements a radar target emulator to evaluate the performance of the radar.

Open Example

Frequency Hopping Using Xilinx RFSoC Device

Design and implement frequency hopping algorithm using Xilinx RF Data Converter numerically controlled oscillator (NCO) real time ports.

Open Example

5G NR SIB1 Recovery for FR1 and FR2 Using Xilinx RFSoC Device

Deploy a 5G NR SIB1 recovery algorithm for FR1 and FR2 in Simulink® using SoC Blockset® to target a Xilinx Zynq® UltraScale+™ RFSoC ZCU111 evaluation board.

Open Example

WLAN Receiver Using Xilinx RFSoC Device

Simulate and deploy a WLAN HDL receiver system and retrieve the signal and data field information from a WLAN signal in Simulink® using an SoC Blockset® implementation targeted on a Xilinx Zynq® UltraScale+™ RFSoC ZCU111 evaluation board. Using this example, you can integrate HDL Implementation of WLAN Receiver (Wireless HDL Toolbox) example into the SoC Blockset implementation.

Open Example

Import Custom HDL IP into SoC Blockset Design

Import an HDL IP and integrate it into an SoC Blockset™ design. In this example, you import the Xilinx® Aurora IP as a Simulink® block and integrate it into a design. You simulate, build and deploy a system that generates and transmits a sinusoidal tone serially using Aurora hardware that first receives the signal from an RF channel. You then loop back the data and visualize the received tone by using an embedded processor.

Open Example

Transmit and Receive Tone Using OTAVA DTRX2 mmWave Radio Card

Integrate an OTAVA DTRX2 mmWave radio card with a Xilinx® Zynq® UltraScale+(TM) RFSoC ZCU208 Evaluation Kit by using SoC Blockset™. In this example, you design, simulate, and deploy a system that generates a sinusoidal tone from an FPGA and transmit the tone in mmWave band through mmWave radio card by using the RF Data Converter (RFDC) and OTAVA DTRX2 blocks. The system then receives the data back into the FPGA by using the OTAVA DTRX2 and RFDC blocks and visualizes the received tone by using an embedded processor.

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