ASCII Encoding/Decoding Resync Loopback Test (With Baseboard Blocks)

This model shows the ability of the FIFO Read HDRS block to resynchronize after being repeatedly disabled as well as the ability to resolve errors such as when a message is only partially complete at the time the read is attempted.

The Switch block alternates between the first and last parts of the message on successive sample times. This mimics a worst case scenario where the model updates before the message construction is complete. As a result, sometimes only part of the message is received. The second pulse generator alternately enables and disables the FIFO Read HDRS block.

Scope 1 graphs the decoded sine wave data received at each time step. When the Pulse Generator1 block outputs a 0, the count from the FIFO Read HDRS block is 0. When it outputs a 1, the read catches up by throwing away extra data and returns the last complete value found in the FIFO. Scope 2 indicates when new data is present.

To test this model:

  1. The target computer must have two COM ports.

  2. Connect COM1 to COM2 with a null modem cable.

This example is configured to use baseboard serial ports (COM1 and COM2). You can also use COM3 and COM4 by changing the board setup in the Baseboard blocks. Other serial blocks could be used in place of the Baseboard blocks. For instance, a single Quatech® 4-port block could be used whereby you send on port 1 and receive on port 2.