How to cater Latency in HDL FFT simulink Block?

I am working on a simulink project and I need to take the FFT using HDL supported block because I need its HDL implementation for FPGA. My input single is of length 11521 x 1 and I want single size point FFT length, for this I keep the FFT length to 16384 which is neareast 2 power factor. Now the issue is that my remaining subsystems processing is optimzed to run for 11521 and i keep stop time of simulation to 11521. With this stop time FFT block doesn't gives o/p as with current i/p single it has latancy of 16514. I can't change the simulation time and i also don't work with lesser FFT sizes. How can I resolve this issue with the help of HDL support block of simulink.

[MULI]

Hi @Hamza

To address this issue in your Simulink project while using HDL-supported blocks for FFT on FPGA, you can consider the following approaches:

• Buffer the Input: Use a buffer to accumulate the input data until you have enough samples to perform a 16384-point FFT. This would mean storing the input data until you reach the desired length.
• Zero Padding: Since your input signal is 11521 samples long, pad the remaining 2863 samples with zeros to reach the FFT length of 16384.

You can also refer to the below link for more information on implementing FFT for FPGA

https://www.mathworks.com/help/dsphdl/gs/generate-hdl-code-for-fft-hdl-optimized-block.html

Answer 1

[Bharath Venkataraman]

You could feed the FFT with 2 samples in at a time (2x1 input) which would then give you 2x1 output and reduce the time needed to comute the output (since it processes two samples at a time).

You could also use a rate transition block to run the FFT at a higher sample rate and feed it with one sample at a time (at the faster rate).