sampling time mismatch in simulink and harware

i am having a simulink model in matlab which is running on sampling time of 5e-6 second now i want to run my matlab file in zedboard which has sampling time of 1e-8 second so both the clock frequency are mismatching.is there any option is available so that i dont need to change the simulink sampling to 1e-8 seconds because my simulink model will not run properly in 1e-8 second

Answer 1

[Leepakshi]

Hi Priyanka,

You don’t need to change your Simulink model to a 1e-8 s sample time. When deploying to ZedBoard using HDL Coder or SoC Blockset, the FPGA runs at its own clock rate, and your Simulink sample time is mapped to hardware through "oversampling" or "rate transition logic".

Options:

• Use "HDL Coder oversampling" factor to match FPGA clock without altering the Simulink design.
• Configure "SoC Blockset task rates" so your algorithm runs at 5e-6 s while the FPGA clock stays at 1e-8 s.
• Avoid forcing the entire model to 1e-8 s; instead, let the tool insert rate converters.

Refer to below links for documentation on Oversampling Factor:

https://www.mathworks.com/help/hdlcoder/ref/oversamplingfactor.html

Hope it helps!

[Priyanka]

Thank you for your response

Answer 2

[Kiran Kintali]

You do not have to model at the FPGA clock rate in the Simulink model. There are several strategies possible.

HDL Coder Evaluation Reference Guide section 2.1 covers notion of FPGA/ASIC clock rate, Simulink sample time and Simulink rate related insights.

https://github.com/mathworks/HDL-Coder-Evaluation-Reference-Guide/blob/main/HDL%20Coder%20Evaluation%20Reference%20Guide%20R2024a.pdf

In addition the following links might be helpful as well.

HDL Coder and RTL Generation:

• https://www.mathworks.com/help/hdlcoder/ug/generating-a-global-oversampling-clock.html
• https://www.mathworks.com/help/hdlcoder/ug/single-precision-field-oriented-control-pmsm-model.html

Hardware Targeting:

• This page https://www.mathworks.com/help/hdlcoder/ug/running-audio-filter-with-multiple-axi4-stream-channels.… has the rate considerations section explaining how you could use the oversampling factor and the example is for a Zedboard.
• This page would be helpful if you want to consider multirate : https://www.mathworks.com/help/hdlcoder/ug/multirate-ip-core-generation.html

[Priyanka]

Thank you for your response