Why do I receive the message "No matching files were found" in HDL Workflow Advisor Step 4.2 "Build FPGA Bitstream"?

Using HDL Workflow Advisor to generate an IP Core for my target, why do I receive the message

Failed No matching files were found

in Step 4.2 "Build FPGA Bitstream"?

Answer 1

[MathWorks Support Team]

This is a generic error message. Most likely, something went wrong during the build in the synthesis tool (e.g. Xilinx Vivado, Intel Quartus). For example, there might be a licensing error with the synthesis tool, or a critical error occurred during the synthesis or implementation.

To find out more about the underlying issue, check the Vivado/Quartus build logs for errors.

The build logs can be accessed by one of the following methods:

1) Open the project files in the respective synthesis tool IDE and check for error messages. For Vivado, the project files can be found at:

hdl_prj/vivado_ip_prj/vivado_prj.xpr

2) In case you did not select "Run build process externally", the build log can be found at:

hdl_prj/hdlsrc/workflow_task_RunSynthesis.log