How to do an HDL Coder design with asynchronous clocks and do resource sharing?

My system has 2 clocks that are asynchronous and are not an integer factor. The data clock is 512 KHz, and the processing (or processor clock) is 200 MHz.

The data is comming from a clock domain crossing FIFO with the output clocked by 200 MHz. The input is data clocked in at 512 KHz. So a new output is available ~every 390.625 200 MHz clocks. But the clocks are asychronous.

I've investigated the streaming and sharing capability but they want an integer factor.

I've investigated a little the triggered sub-systems.

What blocks do I need to do for HDL Coder to automatically do the resource sharing either using streaming or a sharing factors?

What techniques do I need to do for the resource sharing?

Are there examples?

Thanks,

Charlie

Answer 1

[Kiran Kintali]

There are many ways to do this in HDL Coder. You can generate code for each clock domain in a seperate DUT IP core or Model Reference block and stich the code together using blackboxes.

Another option is to use some limited support we have where trigger port of a triggered subsystem can be used as a clock (see attached examples).