Can't generate .bit nor .sof file with FIL Wizard on Ubuntu.

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Eduardo Flores
Eduardo Flores el 27 de Dic. de 2020
Respondida: YP el 21 de Nov. de 2022
After compiling an FPGA in the loop simulink model with VHDL Verifier for Xilinx or Altera devices the new model with the FIL object appears. On windows, a new terminal shows that a new bitstream is being generated but on Ubuntu 18.05, no file is ever created. Am i missing a configuration step?
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Cau Tran
Cau Tran el 11 de Ag. de 2022
I also had this problem. Can anyone give me advice for this one?
FIL does not generate the bitstream file.

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YP
YP el 21 de Nov. de 2022
Can you check if xterm is installed?
FYI https://www.mathworks.com/help/hdlverifier/ug/troubleshooting-fil.html

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