Rider Optimization Algorithm

Binu, D., & Kariyappa, B. S. (2019). RideNN: A New Rider Optimization Algorithm-Based Neural Network for Fault Diagnosis in Analog Circuits. IEEE Transactions on Instrumentation and Measurement, 68(1), 2–26. Institute of Electrical and Electronics Engineers (IEEE). Retrieved from https://doi.org/10.1109%2Ftim.2018.2836058

@article{Binu_2019, doi = {10.1109/tim.2018.2836058}, url = {https://doi.org/10.1109%2Ftim.2018.2836058}, year = 2019, month = {jan}, publisher = {Institute of Electrical and Electronics Engineers ({IEEE})}, volume = {68}, number = {1}, pages = {2--26}, author = {D. Binu and B. S Kariyappa}, title = {{RideNN}: A New Rider Optimization Algorithm-Based Neural Network for Fault Diagnosis in Analog Circuits}, journal = {{IEEE} Transactions on Instrumentation and Measurement} }