Lane Detection on FPGA Reference Application
Learn how to:
- Use Vision HDL Toolbox™ to model a lane detection algorithm in Simulink®
- Auto-generate VHDL code from your Simulink® model and deploy to Speedgoat Simulink-Programmable FPGAs
- Process high-resolution video streams with high sample frequency in real-time
- Directly access video I/O such as HDMI with low latency
Key benefits:
- Build vision-based Advanced Driver Assistance Systems (ADAS) and automated driving systems with hardware-proven subsystems
- Eliminate time-consuming and error-prone steps with automated HDL code generation
- Quickly perform design iterations and test your algorithms continuously
- Bridge the gap between algorithm development and hardware deployment with MATLAB®, Simulink® and Speedgoat hardware solutions
© 2007 – 2020 Speedgoat GmbH
Citar como
Speedgoat Application Engineering Team (2022). Lane Detection on FPGA Reference Application (https://github.com/Speedgoat-Application-Engineering-Team/Lane-Detection-on-FPGA/releases/tag/v1.1.0), GitHub. Recuperado .
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