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Lane Detection on FPGA Reference Application

version 1.1.0 (28 MB) by Speedgoat Application Engineering Team
Learn how to implement a pixel-stream based lane detection algorithm in Simulink, and deploy it to a Speedgoat Simulink-Programmable FPGA.

74 Downloads

Updated 29 Oct 2020

From GitHub

View license on GitHub

Learn how to:
- Use Vision HDL Toolbox™ to model a lane detection algorithm in Simulink®
- Auto-generate VHDL code from your Simulink® model and deploy to Speedgoat Simulink-Programmable FPGAs
- Process high-resolution video streams with high sample frequency in real-time
- Directly access video I/O such as HDMI with low latency

Key benefits:
- Build vision-based Advanced Driver Assistance Systems (ADAS) and automated driving systems with hardware-proven subsystems
- Eliminate time-consuming and error-prone steps with automated HDL code generation
- Quickly perform design iterations and test your algorithms continuously
- Bridge the gap between algorithm development and hardware deployment with MATLAB®, Simulink® and Speedgoat hardware solutions

© 2007 – 2020 Speedgoat GmbH

Cite As

Speedgoat Application Engineering Team (2021). Lane Detection on FPGA Reference Application (https://github.com/Speedgoat-Application-Engineering-Team/Lane-Detection-on-FPGA/releases/tag/v1.1.0), GitHub. Retrieved .

MATLAB Release Compatibility
Created with R2019a
Compatible with R2019a
Platform Compatibility
Windows macOS Linux

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support files/documentation

To view or report issues in this GitHub add-on, visit the GitHub Repository.
To view or report issues in this GitHub add-on, visit the GitHub Repository.