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Michael Du


Last seen: más de 4 años hace |  Con actividad desde 2019

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Rate transitions and HDL generation port requirement
Ferrara, Thank you for your instruction. I have been updating the rate transition at the input or output ports or internal logi...

casi 5 años hace | 0

Respondida
Rate transitions and HDL generation port requirement
The model is attached. To simulate the functionality, it reads in a captured data file and serialize them outside the HDL conver...

casi 5 años hace | 0

Pregunta


Rate transitions and HDL generation port requirement
Due to the down-sampling requirement, the rate transition HDL block is used to sample at a lower rate of the data stream. Also, ...

casi 5 años hace | 4 respuestas | 0

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HDL IP block with more than one type of AXI interface
The idea is to generate the HDL IP blocks using the external PL DDR3 memories with both AXI4 Master and AXIS interfaces. The dat...

casi 5 años hace | 1 respuesta | 0

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AXI4-S interface must use the same sample rate
This question is for the HDL advisor workflow. The AXIS data slave input of the system are taking in data from 3 channels, packa...

casi 5 años hace | 0 respuestas | 0

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Serial port timeout- 10 seconds, but getting less samples than expected/desired
I have similar questions. Matlab seems to set an upper limit to the serial port timeout of ~20ms and the serial input size of 2k...

casi 5 años hace | 0