ChannelCore Flex is an implementation of an array of independent digital down-converters (DDCs) targeted at field programmable gate arrays (FPGAs). The build-time parameterizable architecture allows users to generate bespoke implementations based on their specifications.
Each completely independent channel is runtime-configurable in terms of center frequency (to sub-Hz resolution), output sample rate (to sub–sample-per-second resolution), gain, and output filter response. Spurious-free performance of 80 dB or better is offered as standard. Similar offerings from other FPGA core suppliers use either DDC-based architectures or Fourier transform–based architectures. Individual DDCs offer high levels of channel flexibility, but resource utilization is linearly proportional to the number of channels, making them most suited to applications that require a small numbers of channels. FFT-based architectures have low levels of channel flexibility (all channels have the same or similar bandwidths, frequencies are on a fixed raster, etc.), but resources follow a log(channels) relationship, making them suitable for systems with high channel counts but with proportionally small channel bandwidths.
ChannelCore Flex offers the best of both worlds, so resources follow a log(channels) relationship, but flexibility is like the DDC architecture. This allows a large number of both wideband and narrowband channels to be simultaneously down-converted; the only constraint is that the total bandwidth of all extracted channels is less than or equal to the input bandwidth (higher aggregate bandwidths are available if required at the expense of increased FPGA resource).
ChannelCore Flex is available as an FPGA netlist for implementation, a Mentor Graphics® ModelSim® library for VHDL® simulation, and a fully bit-true MATLAB® model and associated test scripts for both performance verification and generation of test vectors and expected results for VHDL verification.
MATLAB is also used as the design and configuration tool for building variants of ChannelCore Flex. For each variant, a top-level MATLAB script is configured in terms of top-level specification and implementation parameters. This script calls a number of design functions that design all aspects of the core and its submodules. The outputs of the design function(s) are VHDL packages, a binary configuration file that is used to configure the MATLAB model, and any other supporting files, such as VHDL stimulus and reference.