HDL Coder

Key Features

  • Target-independent, synthesizable VHDL and Verilog code
  • Code generation support for MATLAB functions, System objects, and Simulink blocks
  • Mealy and Moore finite-state machines and control logic implementations using Stateflow
  • Workflow advisor for programming Xilinx, Microsemi, and Intel application boards
  • Resource sharing and retiming for area-speed tradeoffs
  • Code-to-model and model-to-code traceability for DO-254
  • Legacy code integration

Generating HDL code from MATLAB or Simulink with HDL Coder. You can generate synthesizable VHDL and Verilog code from MATLAB functions, Simulink models, or a combination of the two.

Generating HDL Code

HDL Coder lets you generate synthesizable HDL code for FPGA and ASIC implementations in a few steps:

HDL Coder generates readable, traceable, synthesizable VHDL or Verilog HDL.

Documenting and Tracing HDL Code

HDL Coder produces readable VHDL® and Verilog® code, re-using naming conventions from your MATLAB and Simulink functions and blocks. When generating HDL code, you can create a traceability report, which is an HTML report that links from the generated HDL code back to its MATLAB or Simulink origin.

For high-integrity workflows such as DO-254, you can combine the HDL Coder traceability report with Simulink Requirements to trace your HDL code back to the system requirements from which it originated.

HDL Coder generates VHDL and Verilog that meets popular industry coding guidelines such as RMM and STARC. It generates scripts to analyze its output using third-party lint tools. You can use the Simulink Model Advisor during the design phase, and create reports when generating HDL code to identify unsuitable constructs in your design so that you can adapt your models to satisfy these guidelines.

Designing for HDL Code Generation

When targeting algorithms to hardware, you need to modify them to process streams of bits rather than blocks of data. Typical steps include managing the data stream, parallelizing operations, managing the timing of parallel paths, and ensuring that the implementation fits within the device’s available resources.

Use the strengths of MATLAB® and Simulink® to deploy an algorithm to hardware.

HDL-Optimized Blocks and System objects

HDL Coder supports more than 200 Simulink blocks, and it lets you set HDL-specific implementation properties. You can use additional application-specific, HDL-optimized blocks, including:

Floating- and Fixed-Point Data

FPGA and ASIC hardware are composed of fixed resources, so you need to manage data word lengths to meet performance requirements and use resources efficiently. However, this is difficult when you need to convert algorithms developed using double-precision floating-point arithmetic to fixed-point implementations while still maintaining sufficient mathematical accuracy.

HDL Coder Native Floating Point lets you generate synthesizable VHDL or Verilog directly from single-precision Simulink models. This helps you start targeting FPGAs more quickly. Even as you convert most of your design to fixed-point so you can implement it more efficiently, you can isolate operations that need to be implemented as Native Floating Point. This is typically the most efficient approach for mathematical equations that require a high-dynamic range such as flux equations, cumulative distribution functions, and state-space equations.

Fixed-Point Designer™ automates and manages the fixed-point conversion process. It uses simulation data to propose word lengths and precision requirements for each operation in your design. These settings can be applied as proposed, or you can override the proposals with your own settings.

HDL Coder provides options to best suit the data types you need. Fixed-Point Designer automates the conversion process to fixed-point. HDL Coder generates vendor-independent native floating point HDL and targets vendor-specific floating point hard or soft IP blocks.

Getting Started Resources

To start adapting your algorithm for HDL code generation, download the HDL Coder Evaluation Reference Guide.

If you are new to FPGA design, the DSP for FPGAs training course covers the hardware implementation tradeoffs of targeting various signal processing algorithms to FPGA devices. And you can choose from a variety of Consulting Services offerings, from implementing HDL-ready designs to receiving methodology assistance.

Optimizing HDL Code

HDL Coder helps you optimize your code whether you are targeting hardware for prototyping or for production. Its set of optimization options works automatically or with your guidance. To increase your design’s clock frequency and maintain its functionality, HDL Coder inserts and distributes pipeline registers while balancing parallel paths. To reduce the area and power of your design, HDL Coder can convert parallel structures to serial structures and share resources. Many of the HDL-ready blocks and System objects, such as filters and math operations, come with customization options.

Designing at the architectural level allows you to more broadly explore the speed and size impact that techniques such as vector processing, oversampling, and region-of-interest processing have on your design. This means you can generate higher-quality code than if you manually coded HDL, because you have the freedom to explore a broader range of solutions.

Nokia improves FPGA and ASIC quality through this type of exploration and optimization:

Optimizing at the architectural level allows you to more broadly explore implementation options.

FPGA Prototyping

Engineers often use HDL Coder to prototype applications on FPGA hardware for high-speed, real-world validation. Targeting an FPGA or SoC device on a board requires that the model’s inputs and outputs are mapped to device- and board- specific interfaces. HDL Coder offers built-in targets to automatically configure popular FPGA prototyping systems.

Prototype on a Xilinx Zynq-7000 All Programmable SoC board with an RF FMC card or PicoZed SDR to test your design using live over-the-air signals.

Hardware Support Packages

To automate setup and targeting for popular development kits from Xilinx® and Intel® (formerly Altera), you can download the HDL Coder hardware support package for your device family.

You can also download application-specific hardware support packages that support FPGA targeting for software-defined radio (SDR), motor control, and vision processing.

Real-Time Simulation and Testing with Simulink Real-Time and Speedgoat FPGA Technology

To perform high-speed prototyping of controls, DSP, vision, and plant simulation projects with hardware-in-the-loop (HIL), you’ll often need FPGAs for low latency and fast computation. Simulink Real-Time™, together with programmable FPGA I/O modules from Speedgoat, provide a low-latency platform for applications requiring up to hundreds of I/O lines. Using the built-in settings in HDL Workflow Advisor, you can automate targeting the FPGA I/O modules. Native Floating Point HDL code generation further eases FPGA targeting, especially for high-dynamic range operations. Integrated data logging, monitoring, and real-time tuning help you rapidly iterate on and debug your designs.

Deploying to Production FPGA, SoC, or ASIC

When you are ready to deploy your design to a production device, HDL Coder offers robust options for mapping to chip-level inputs and outputs (I/O). You can also map to system-on-chip (SoC) interfaces commonly used for hardware-software implementations.

You can define a custom reference design with your board-level interfaces, and register it with HDL Coder. During HDL code generation, you can then select it as the target and define how your design’s I/O maps to other components on the board, off the board, or to AXI interfaces such as memory controllers or system busses.

For generating a subsystem for an FPGA or ASIC SoC, the IP core generation workflow target lets you map its ports to chip-level I/O or a variety of AXI interconnect protocols, including AXI4, AXI4-Lite, AXI4-Master, and AXI4-Stream for Video.

You can use HDL Coder for production deployment of a wide variety of applications. Examples include:

Map algorithm inputs and outputs to board-level or AXI bus interfaces for production deployment.

Verifying HDL Code

HDL Coder generates VHDL and Verilog test benches for rapid verification of generated HDL code. You can customize an HDL test bench using a variety of options that apply stimuli to the HDL code and check its results. You can also generate script files to automate the process of compiling and simulating your code in HDL simulators.

HDL Coder works with HDL Verifier to automatically generate two types of cosimulation models:

  • HDL cosimulation model, for cosimulating Simulink with HDL simulators, including Cadence Incisive and Mentor Graphics ModelSim and Questa
  • FPGA-in-the-loop (FIL) cosimulation model, for verifying your design with Simulink and an FPGA board.

HDL Coder generates readable, traceable, synthesizable VHDL or Verilog HDL.

Incorporating HDL Code Generation in Model-Based Design

Model-Based Design links requirements, system design, implementation, and testing. This approach lets members of your design team collaborate with each other. As you partition the portion of your design targeted for hardware, you can re-use your system-level verification infrastructure and tests. You can refine your model to add hardware implementation details and fixed-point quantization. Model-Based Design offers full support for revision control and traceability.

Allegro Microsystems deploys Model-Based Design for mixed-signal ASIC design and implementation:

A Model-Based Design workflow for refining algorithmic design to a fixed-point hardware implementation. You can generate models from this implementation and use them for downstream workflows.