In this webinar, you will learn how to leverage HDL Coder to explore design choices tuned to specific speed and area constraints. Using HDL Coder, you can invoke several optimization features that allow you to share hardware resources for reduced area footprint and features that allow you to pipeline your design to improve the design’s clock frequency.
MathWorks engineers will demonstrate the latest enhancements to HDL Coder, which enable an iterative workflow to explore the speed/area design space when generating synthesizable Verilog and VHDL from Simulink models, MATLAB code and Stateflow charts.
We will discuss the following topics:
- Area Optimizations
- Basic area optimization workflow
- Resource sharing Simulink blocks and MATLAB code
- RAM Mapping: mapping MATLAB matrices to FPGA block RAMs
- Loop Streaming: efficient implementation of MATLAB ‘for’ loops and matrix operations
- Speed Optimizations
- Basic speed optimization workflow
- Back-annotation: visualize post-synthesis and post-mapping critical path in Simulink
- Inserting pipeline registers in Simulink models and MATLAB code
- Distributed Pipelining: an automated optimization based on retiming
About the Presenter: Girish Venkataramani is the team lead for the HDL Optimizations and HW/SW Co-design group. He has been working on the HDL Coder product since 2007 and is the chief architect of the compiler infrastructure and HDL (speed/area) optimizations framework of the product. Prior to joining MathWorks, Girish worked on several research problems involving different C-to-HDL compiler tools. He holds a Ph.D. in electrical and computer engineering from Carnegie Mellon University, where he explored performance analysis and optimization problems within an asynchronous C-to-HDL compiler. He holds an M.S. in Computer Science from University of California Riverside.
