Convolutional Deinterleaver

Restore ordering of symbols that were permuted using shift registers

Library

Convolutional sublibrary of Interleaving

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Description

The Convolutional Deinterleaver block recovers a signal that was interleaved using the Convolutional Interleaver block. Internally, this block uses a set of shift registers. The parameters in the two blocks must have the same values. For information about delays, see Delays of Convolutional Interleaving and Deinterleaving.

This block accepts a scalar or column vector input signal, which can be real or complex. The output signal has the same sample time as the input signal.

This block accepts the following data types: int8, uint8, int16, uint16, int32, uint32, boolean, single, double, and fixed-point.

Parameters

Rows of shift registers

The number of shift registers that the block uses internally.

Register length step

The difference in symbol capacity of each successive shift register, where the last register holds zero symbols.

Initial conditions

Indicates the values that fill each shift register at the beginning of the simulation (except for the last shift register, which has zero delay).

• When you select a scalar value for Initial conditions, the value fills all shift registers (except for the last one)

• When you select a column vector with a length equal to the Rows of shift registers parameter, each entry fills the corresponding shift register.

The value of the first element of the Initial conditions parameter is unimportant, since the last shift register has zero delay.

Examples

For an example that uses this block, see Convolutional Interleaving.

Pair Block

Convolutional Interleaver

More About

Delays of Convolutional Interleaving and Deinterleaving

The total delay due to a convolutional interleaver and deinterleaver pair is N × slope × (N – 1).

• N is the number of registers and equals the value of the Rows of shift registers parameter

• slope is the register length step and equals the value of the Register length step parameter

This diagram shows the structure of a general convolutional interleaver comprised of a set of shift registers, each having a specified delay shown as D(1), D(2),..., D(N), and a commutator to switch input and output symbols through registers. The kth shift register holds D(k) symbols, where k = 1, 2, 3, … N. The kth shift register has a delay value of ((k–1) × slope). With each new input symbol, the commutator switches to a new register and shifts in the new symbol while shifting out the oldest symbol in that register. When the commutator reaches the Nth register, upon the next new input, the commutator returns to the first register.

References

[1] Clark, George C., and J. Bibb Cain. Error-Correction Coding for Digital Communications. Applications of Communications Theory. New York: Plenum Press, 1981.

[2] Forney, G., D., Jr. "Burst-Correcting Codes for the Classic Bursty Channel." IEEE Transactions on Communications, vol. COM-19, October 1971. 772-781.

[3] Ramsey, J. L. "Realization of Optimum Interleavers." IEEE Transactions on Information Theory, IT-16 (3), May 1970. 338-345.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

You can generate HDL code for the Convolutional Deinterleaver block using a shift-register-based implementation, or a RAM-based implementation.

The default implementation for the Convolutional Deinterleaver block is shift register-based. To suppress generation of reset logic, set the implementation parameter ResetType to'none'. When you set ResetType to'none', reset is not applied to the shift registers.

When registers are not fully loaded, mismatches between Simulink^® and the generated code occur for some number of samples during the initial phase. To avoid spurious test bench errors, determine the number of samples required to fill the shift registers. Set the Ignore output data checking (number of samples) option accordingly. (If you are using the command-line interface, you can use the IgnoreDataChecking property for this purpose.)

When you select the RAM implementation for a Convolutional Deinterleaver block, HDL Coder uses RAM resources instead of shift registers.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).
ResetType	Suppress reset logic generation. The default is default, which generates reset logic. See also ResetType (HDL Coder).

Restrictions

When you select the RAM implementation:

• Double or single data types are not supported for either input or output signals.

• You must set Initial conditions for the block to zero.

• At least two rows of interleaving are required.

Version History

Introduced before R2006a