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CIC Decimator

Decimate signal using CIC filter

  • Library:
  • DSP HDL Toolbox / Filtering

  • CIC Decimator block

Description

The CIC Decimator block decimates an input signal by using a cascaded integrator-comb (CIC) decimation filter. CIC decimation filters are a class of linear phase finite impulse response (FIR) filters consisting of a comb part and an integrator part. The CIC decimation filter structure consists of N sections of cascaded integrators, a rate change factor of R, and N sections of cascaded comb filters. For more information about CIC decimation filters, see Algorithms.

The block supports these combinations of input and output data.

  • Scalar input and scalar output — Support for fixed and variable decimation rates

  • Vector input and scalar output — Support for fixed decimation rates only

  • Vector input and vector output — Support for fixed decimation rates only

The block provides an architecture suitable for HDL code generation and hardware deployment.

Ports

Input

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Input data, specified as a scalar or a column vector with a length from 1 to 64. The input data must be a signed integer or a signed fixed point with a word length less than or equal to 32. The Decimation factor (R) parameter must be an integer multiple of the input frame size.

Data Types: int8 | int16 | int32 | signed fixed point
Complex Number Support: Yes

Control signal that indicates if the input data is valid. When valid is 1 (true), the block captures the values from the input data port. When valid is 0 (false), the block ignores the values from the input data port.

Data Types: Boolean

Use this port to dynamically specify the variable decimation rate during run time.

This value must have the data type fixdt(0,12,0) and it must be an integer in the range from 1 to the Decimation factor (Rmax) parameter value.

Dependencies

To enable this port, on the Main tab, set the Decimation factor source parameter to Input port.

Data Types: fixdt(0,12,0)

Control signal that clears internal states. When reset is 1 (true), the block stops the current calculation and clears internal states. When the reset is 0 (false) and the input valid is 1 (true), the block captures data for processing.

For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.

Dependencies

To enable this port, on the Control Ports tab, select the Enable reset input port parameter.

Data Types: Boolean

Output

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The block returns filtered output data as a scalar or a column vector with a length from 1 to 64. You can define the data type of this output by setting the Output data type parameter on the Data Types tab.

Data Types: int8 | int16 | int32 | signed fixed point
Complex Number Support: Yes

Control signal that indicates if the data from the output data port is valid. When valid is 1 (true), the block returns valid data from the output data port. When valid is 0 (false), the values from the output data port are not valid.

Data Types: Boolean

Parameters

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Main

Select whether the block operates with a fixed or variable decimation rate.

  • Property — Use a fixed decimation rate specified from the Decimation factor (R) parameter.

  • Input port — Use a variable decimation rate specified from the R input port.

Note

For vector inputs, the block does not support variable decimation.

Specify the decimation factor rate at which the block decimates the input.

Dependencies

To enable this parameter, set the Decimation factor source parameter to Property.

Specify the upper bound of the range of valid values for the R input port.

Note

For vector inputs, the block does not support variable decimation.

Dependencies

To enable this parameter, set the Decimation factor source parameter to Input port.

Specify the differential delay of the comb part of the block.

Specify the number of sections in either the comb part or the integrator part of the block.

Select this parameter to compensate for the output gain of the block.

The latency of the block changes depending on the type of input, the decimation you specify, the number of sections, and the value of this parameter. For more information on the latency of the block, see Latency.

Data Types

Select the data type for the output data.

  • Full precision — The output data type has a word length equal to the input word length plus gain bits.

  • Same word length as input — The output data type has a word length equal to the input word length.

  • Minimum section word lengths — The output data type uses the word length you specify in the Output word length parameter. When you select this option, the block applies the pruning algorithm. For more information about the pruning algorithm, see [1].

Specify the word length of the output.

Note

When this value is 2, 3, 4, 5, or 6, the block can overflow the output data.

Dependencies

To enable this parameter, set the Output data type parameter to Minimum section word lengths.

Control Ports

Select this parameter to enable the reset input port. The reset signal implements a local synchronous reset of the data path registers.

For more reset considerations, see Tips.

Select this parameter to connect the generated HDL global reset signal to the data path registers. This parameter does not change the appearance of the block or modify simulation behavior in Simulink®. When you clear this parameter, the generated HDL global reset clears only the control path registers. The generated HDL global reset can be synchronous or asynchronous depending on the HDL Code Generation > Global Settings > Reset type parameter in the model Configuration Parameters.

For more reset considerations, see Tips.

Tips

Reset Behavior

  • By default, the CIC Decimator block connects the generated HDL global reset to only the control path registers. The two reset parameters, Enable reset input port and Use HDL global reset, connect a reset signal to the data path registers. Because of the additional routing and loading on the reset signal, resetting data path registers can reduce synthesis performance.

  • The Enable reset input port parameter enables the reset port on the block. The reset signal implements a local synchronous reset of the data path registers. For optimal use of FPGA resources, this option does not connect the reset signal to registers targeted to the DSP blocks of the FPGA.

  • The Use HDL global reset parameter connects the generated HDL global reset signal to the data path registers. This parameter does not change the appearance of the block or modify simulation behavior in Simulink. The generated HDL global reset can be synchronous or asynchronous depending on the HDL Code Generation > Global Settings > Reset type parameter in the model Configuration Parameters. Depending on your device, using the global reset might move registers out of the DSP blocks and increase resource use.

  • When you select the Enable reset input port and Use HDL global reset parameters together, the global and local reset signals clear the control and data path registers.

Reset Considerations for Generated Test Benches

  • FPGA-in-the-loop (FIL) initialization provides a global reset but does not automatically provide a local reset. With the default reset parameters, the data path registers that are not reset can result in FIL mismatches if you run the FIL model more than once without resetting the board. Select Use HDL global reset to reset the data path registers automatically, or select Enable reset input port and assert the local reset in your model so the reset signal becomes part of the Simulink FIL test bench.

  • The generated HDL test bench provides a global reset but does not automatically provide a local reset. With the default reset parameters and the default register reset Configuration Parameters, the generated HDL code includes an initial simulation value for the data path registers. However, if you are concerned about X-propagation in your design, you can set the HDL Code Generation > Global Settings > Coding style > No-reset register initialization parameter in Configuration Parameters to Do not initialize. In this case, with the default block reset parameters, the data path registers that are not reset can cause X-propagation on the data path at the start of HDL simulation. Select Use HDL global reset to reset the data path registers automatically, or select Enable reset input port and assert the local reset in your model so the reset signal becomes part of the generated HDL test bench.

Algorithms

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References

[1] Hogenauer, E. “An Economical Class of Digital Filters for Decimation and Interpolation.” IEEE Transactions on Acoustics, Speech, and Signal Processing 29, no. 2 (April 1981): 155–62. https://doi.org/10.1109/TASSP.1981.1163535.

Extended Capabilities

Version History

Introduced in R2019b

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