AXI4-Interface Write
Write data to IP core on AMD SoC Device
Add-On Required: This feature requires the Embedded Coder Support Package for AMD SoC Devices add-on.
Description
This block writes a data vector to a contiguous group of memory-mapped registers on an HDL Coder™ generated IP core. The AXI4-Interface Write block, using the central interconnect of the processing system, provides simple memory-mapped communication with the IP core on the FPGA. This block is best suited for low-throughput communication, such as setting status, state, or control registers. This diagram shows the path of the data after it leaves this block.
Ports
Input
Parameters
Version History
Introduced in R2013a