bitandreduce

Reduce consecutive slice of bits to one bit by performing bitwise AND operation

Syntax

c = bitandreduce(a)

c = bitandreduce(a, lidx)

c = bitandreduce(a, lidx, ridx)

Description

c = bitandreduce(a) performs a bitwise AND operation on the entire set of bits in the fixed-point input, a, and returns the result as an unsigned integer of word length 1.

c = bitandreduce(a, lidx) performs a bitwise AND operation on a consecutive range of bits, starting at position lidx and ending at the LSB (the bit at position 1).

c = bitandreduce(a, lidx, ridx) performs a bitwise AND operation on a consecutive range of bits, starting at position lidx and ending at position ridx.

The bitandreduce arguments must satisfy the following condition:

a.WordLength >= lidx >= ridx >= 1

Examples

Perform Bitwise AND Operation on an Entire Set of Bits

Create a fixed-point number.

a = fi(73,0,8,0);
disp(bin(a))

01001001

Perform a bitwise AND operation on the entire set of bits in a.

c = bitandreduce(a)

c = 
     0

          DataTypeMode: Fixed-point: binary point scaling
            Signedness: Unsigned
            WordLength: 1
        FractionLength: 0

Because the bits of a do not all have a value of 1, the output has a value of 0.

Perform Bitwise AND Operation on a Range of Bits in a Vector

Create a fixed-point vector.

a = fi([12, 4, 8, 15],0,8,0);
disp(bin(a))

00001100   00000100   00001000   00001111

Perform a bitwise AND operation on the bits of each element of a, starting at position fi(4).

c = bitandreduce(a, fi(4))

c = 
     0     0     0     1

          DataTypeMode: Fixed-point: binary point scaling
            Signedness: Unsigned
            WordLength: 1
        FractionLength: 0

The only element in output c with a value of 1 is the 4th element. This is because it is the only element of a that had only 1's between positions fi(4) and 1.

Perform Bitwise AND Operation on a Range of Bits in a Matrix

Create a fixed-point matrix.

a = fi([7, 8, 1; 5, 9, 5; 8, 37, 2], 0, 8, 0);
disp(bin(a))

00000111   00001000   00000001
00000101   00001001   00000101
00001000   00100101   00000010

Perform a bitwise AND operation on the bits of each element of matrix a beginning at position 3 and ending at position 1.

c = bitandreduce(a, 3, 1)

c = 
     1     0     0
     0     0     0
     0     0     0

          DataTypeMode: Fixed-point: binary point scaling
            Signedness: Unsigned
            WordLength: 1
        FractionLength: 0

There is only one element in output c with a value of 1. This condition occurs because the corresponding element in a is the only element with only 1's between positions 3 and 1.

Input Arguments

a — Input array

scalar | vector | matrix | multidimensional array

Input array, specified as a scalar, vector, matrix, or multidimensional array of fi objects.

bitandreduce supports both signed and unsigned inputs with arbitrary scaling. The sign and scaling properties do not affect the result type and value. bitandreduce performs the operation on a two's complement bit representation of the stored integer.

Data Types: fixed-point fi

lidx — Start position of range

scalar

Start position of range specified as a scalar of built-in type. lidx represents the position in the range closest to the MSB.

Data Types: fi|single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64

ridx — End position of range

scalar

End position of range specified as a scalar of built-in type. ridx represents the position in the range closest to the LSB (the bit at position 1).

Data Types: fi|single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64

Output Arguments

c — Output array

scalar | vector | matrix | multidimensional array

Output array, specified as a scalar, vector, matrix, or multidimensional array of fixed-point fi objects. c is unsigned with word length 1.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using MATLAB® Coder™.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

For VHDL^®, generates the bitwise AND operator operating on a set of individual slices.

For Verilog^®, generates the reduce operator:

&a[lidx:ridx]

Version History

Introduced in R2007b