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Balance delays for generated DUT input ports

Insert matching delays on generated DUT inport port paths

Since R2022b

Model Configuration Pane: Global Settings / Ports

Description

Enable this setting to insert matching delays on generated DUT inport port paths. Disable this setting to prevent HDL Coder™ from inserting matching delays on paths with stable inputs. Disable this setting if you do not intend to change the tunable parameter associated with the generated DUT input port while running your design on hardware. Preventing matching delays on stable paths in the DUT reduces the amount of resources needed for your design.

Dependencies

To disable this parameter, select the Enable HDL DUT input port generation for tunable parameters check box.

Settings

on (default) | off

Default: On

on

HDL Coder inserts matching delays on the path of generated DUT input ports for tunable parameters signals in the generated HDL code.

off

HDL Coder does not insert matching delays on the path of generated DUT input ports for tunable parameters signals in the generated HDL code.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, after you designate signals as tunable parameters for the sfir_fixed/symmetric_fir DUT subsystem, to prevent matching delays on the generated DUT input port path in the HDL code, use either of these methods:

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_sfir',...
    'BalanceDelaysForTunableParam','off')

  • When you use hdlset_param, you can set the parameter on the model, and then generate HDL code by using makehdl.

    hdlset_param('sfir_fixed','BalanceDelaysForTunableParam','off')
makehdl('sfir_fixed/symmetric_fir')

Recommended Settings

No recommended settings.

Programmatic Use

Parameter: BalanceDelaysForTunableParam
Type: character vector
Value: 'on' | 'off'
Default: 'on'

Version History

Introduced in R2022b

See Also