Clock enable input port
Name for clock enable input port
Model Configuration Pane: Global Settings
Description
Specify the name for the clock enable input port in generated HDL code.
Settings
clk_enable
(default) | character vectorDefault: clk_enable
Enter the clock enable input port name in generated HDL code as a character vector.
For example, if you specify 'filter_clock_enable'
for the generating subsystem filter_subsys
, the generated entity declaration might look as follows:
ENTITY filter_subsys IS PORT( clk : IN std_logic; filter_clock_enable : IN std_logic; reset : IN std_logic; filter_subsys_in : IN std_logic_vector (15 DOWNTO 0); filter_subsys_out : OUT std_logic_vector (15 DOWNTO 0); ); END filter_subsys;
The clock enable input signal is asserted active-high (1). Thus, the input value must be high for the generated entity's registers to be updated.
If you specify a VHDL®, Verilog® or SystemVerilog reserved word, the code generator appends a reserved word postfix string to form a valid VHDL, Verilog or SystemVerilog identifier. For example, if you specify the reserved word signal
, the resulting name string would be signal_rsvd
.
Tips
To set this property, use the functions hdlset_param
or makehdl
. To view the property value, use
the function hdlget_param
.
For example, you can specify this property when you generate HDL code for the symmetric_fir
subsystem inside the sfir_fixed
model using either of these methods.
Pass the property as an argument to the
makehdl
function.makehdl('sfir_fixed/symmetric_fir', ... 'ClockEnableInputPort','clken')
When you use
hdlset_param
, you can set the parameter on the model and then generate HDL code usingmakehdl
.hdlset_param('sfir_fixed','ClockEnableInputPort','clken') makehdl('sfir_fixed/symmetric_fir')
Recommended Settings
No recommended settings.
Programmatic Use
Parameter: ClockEnableInputPort |
Type: character vector |
Value: A valid identifier in the target language |
Default: 'clk_enable' |
Version History
Introduced in R2012a
See Also
makehdl
| Clock enable output port | Clock input port | Reset input port