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Clock high time (ns)

Specify the period, in nanoseconds, during which the test bench drives clock input signals high (1)

Model Configuration Pane: Test Bench

Description

Specify the period, in nanoseconds, during which the test bench drives clock input signals high (1).

Dependencies

This parameter is enabled when Force clock is selected.

Settings

5 (default)

Specify a positive integer value. The Clock high time and Clock low time properties define the period and duty cycle for the clock signal. Using the defaults, the clock signal is a square wave (50% duty cycle) with a period of 10 ns.

Recommended Settings

No recommendations.

Programmatic Use

Parameter: ClockHighTime
Type: integer
Value: positive integer
Default: 5

Tips

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can specify this parameter for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdltb function.

    makehdltb('sfir_fixed/symmetric_fir', ... 
            'ClockHighTime', 2)

  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdltb.

    hdlset_param('sfir_fixed', 'ClockHighTime', 2)
makehdltb('sfir_fixed/symmetric_fir')

Version History

Introduced in R2012a