makehdltb

Generate HDL test bench from model or subsystem

Syntax

makehdltb(dut)

makehdltb(dut,Name,Value)

Description

makehdltb(dut) generates an HDL test bench from the specified subsystem or model reference.

makehdltb(dut,Name,Value) generates an HDL test bench from the specified subsystem or model reference with options specified by one or more name-value pair arguments.

Note

• If you have not previously executed makehdl within the current MATLAB^® session, makehdltb calls makehdl to generate model code before generating the test bench code. Properties passed in to makehdl persist after makehdl executes, and (unless explicitly overridden) are passed to subsequent makehdltb calls during the same MATLAB session.

• Test bench code and model code must both be generated in the same target language. If the target language specified for makehdltb differs from the target language specified for the previous makehdl execution, makehdltb regenerates model code in the same language specified for the test bench.

Examples

Generate VHDL Test Bench

Generate VHDL^® DUT and test bench for a subsystem.

Use makehdl to generate VHDL code for the subsystem symmetric_fir.

makehdl('sfir_fixed/symmetric_fir')

### Generating HDL for 'sfir_fixed/symmetric_fir'.
### Starting HDL check.
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings, 
    and 0 messages.
### Begin VHDL Code Generation for 'sfir_fixed'.
### Working on sfir_fixed/symmetric_fir as 
    hdlsrc\sfir_fixed\symmetric_fir.vhd
### HDL code generation complete.

After makehdl is complete, use makehdltb to generate a VHDL test bench for the same subsystem.

makehdltb('sfir_fixed/symmetric_fir')

### Begin TestBench generation.
### Generating HDL TestBench for 'sfir_fixed/symmetric_fir'.
### Begin simulation of the model 'gm_sfir_fixed'...
### Collecting data...
### Generating test bench: hdlsrc\sfir_fixed\symmetric_fir_tb.vhd
### Creating stimulus vectors...
### HDL TestBench generation complete.

The generated VHDL test bench code is saved in the hdlsrc folder.

Generate Verilog Test Bench

Generate Verilog^® DUT and test bench for a subsystem.

Use makehdl to generate Verilog code for the subsystem symmetric_fir.

makehdl('sfir_fixed/symmetric_fir','TargetLanguage','Verilog')

### Generating HDL for 'sfir_fixed/symmetric_fir'.
### Starting HDL check.
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings, 
    and 0 messages.
### Begin Verilog Code Generation for 'sfir_fixed'.
### Working on sfir_fixed/symmetric_fir as 
    hdlsrc\sfir_fixed\symmetric_fir.v
### HDL code generation complete.

After makehdl is complete, use makehdltb to generate a Verilog test bench for the same subsystem.

makehdltb('sfir_fixed/symmetric_fir','TargetLanguage','Verilog')

### Begin TestBench generation.
### Generating HDL TestBench for 'sfir_fixed/symmetric_fir'.
### Begin simulation of the model 'gm_sfir_fixed'...
### Collecting data...
### Generating test bench: hdlsrc\sfir_fixed\symmetric_fir_tb.v
### Creating stimulus vectors...
### HDL TestBench generation complete.

The generated Verilog test bench code is saved in the hdlsrc\sfir_fixed folder.

Generate SystemVerilog Test Bench

Generate SystemVerilog DUT and test bench for a subsystem.

Use makehdl to generate SystemVerilog code for the subsystem symmetric_fir.

makehdl('sfir_fixed/symmetric_fir','TargetLanguage','SystemVerilog')

After makehdl is complete, use makehdltb to generate a SystemVerilog test bench for the same subsystem.

makehdltb('sfir_fixed/symmetric_fir','TargetLanguage','SystemVerilog')

The generated SystemVerilog test bench code for the symmetric_fir subsystem is saved in the hdlsrc\sfir_fixed\symmetric_fir_tb.sv.

Generate a SystemVerilog DPI Test Bench

Generate SystemVerilog DPI test bench for a subsystem.

Consider this option if generation or simulation of the default HDL test bench takes a long time. Generation of a DPI test bench can be faster than the default version because it does not run a Simulink^® simulation to create the test bench data. Simulation of a DPI test bench with a large data set is faster than the default version because it does not store the input or expected data in a separate file. For requirements to use this feature, see the GenerateSVDPITestBench property.

Use makehdl to generate Verilog code for the subsystem symmetric_fir.

makehdl('sfir_fixed/symmetric_fir','TargetLanguage','Verilog')

### Generating HDL for 'sfir_fixed/symmetric_fir'.
### Starting HDL check.
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings, 
    and 0 messages.
### Begin Verilog Code Generation for 'sfir_fixed'.
### Working on sfir_fixed/symmetric_fir as 
    hdlsrc\sfir_fixed\symmetric_fir.v
### HDL code generation complete.

After the code is generated, use makehdltb to generate a test bench for the same subsystem. Specify your HDL simulator so that the code generator can generate scripts to build and run the generated SystemVerilog and C code. Disable generation of the default test bench.

makehdltb('sfir_fixed/symmetric_fir','TargetLanguage','Verilog',...
      'GenerateSVDPITestBench','ModelSim','GenerateHDLTestBench','off')

### Start checking model compatibility with SystemVerilog DPI testbench
### Finished checking model compatibility with SystemVerilog DPI testbench
### Preparing generated model for SystemVerilog DPI component generation
### Generating SystemVerilog DPI component
### Starting build procedure for model: gm_sfir_fixed_ref
### Starting SystemVerilog DPI Component Generation
### Generating DPI H Wrapper gm_sfir_fixed_ref_dpi.h
### Generating DPI C Wrapper gm_sfir_fixed_ref_dpi.c
### Generating SystemVerilog module gm_sfir_fixed_ref_dpi.sv using template C:\matlab\toolbox\hdlverifier\dpigenerator\rtw\hdlverifier_dpitb_template.vgt
### Generating makefiles for: gm_sfir_fixed_ref_dpi
### Invoking make to build the DPI Shared Library
### Successful completion of build procedure for model: gm_sfir_fixed_ref
### Working on symmetric_fir_dpi_tb as hdlsrc\sfir_fixed\symmetric_fir_dpi_tb.sv.
### Generating SystemVerilog DPI testbench simulation script for ModelSim/QuestaSim hdlsrc\sfir_fixed\symmetric_fir_dpi_tb.do

### HDL TestBench generation complete.

The generated SystemVerilog and C test bench files, and the build scripts, are saved in the hdlsrc\sfir_fixed folder.

Input Arguments

dut — DUT subsystem or model reference name

character vector

DUT subsystem or model reference name, specified as a character vector, with full hierarchical path.

Example: 'modelname/subsysTarget'

Example: 'modelname/subsysA/subsysB/subsysTarget'

Name-Value Arguments

Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

Before R2021a, use commas to separate each name and value, and enclose Name in quotes.

Example: 'TargetLanguage','Verilog'

Target Language and Folder Selection Options

HDLSubsystem — DUT Subsystem

character vector

Specify the Subsystem in your model to generate the test bench for. For more information, see Generate HDL for.

TargetLanguage — Target language

'VHDL' (default) | 'Verilog' | 'SystemVerilog'

Specify whether to generate VHDL or Verilog code. For more information, see Language.

TargetDirectory — Output directory

'hdlsrc' (default) | character vector

Specify a path to write the generated files and HDL code into. For more information, see Code Generation Folder.

Test Bench Generation Output Options

SimulationTool — HDL simulator where you will run the generated test bench

'Mentor Graphics ModelSim' (default) | 'Cadence Incisive' | 'Synopsys VCS' | 'Xilinx Vivado Simulator' | 'Custom'

This property applies to generated test benches. When you select 'Custom', the tool uses the custom script settings. See the “Script Generation” properties.

For more information, see Simulation tool.

HDLCodeCoverage — Enable code coverage on the generated test bench

'off' (default) | 'on'

Include code coverage switches in the generated build-and-run scripts. These switches turn on code coverage for the generated test bench. Specify your HDL simulator in the SimulationTool property. The code generator produces build-and-run scripts for the simulator you specify.

When the GenerateCoSimModel argument is set to Xilinx Vivado Simulator, code coverage is not supported, and this input is ignored.

For more information, see HDL code coverage.

GenerateHDLTestBench — Generate HDL test bench

'on' (default) | 'off'

The code generator produces an HDL test bench by running a Simulink simulation to capture input vectors and expected output data for your DUT. For more information, see HDL test bench.

GenerateSVDPITestBench — Generate SystemVerilog DPI test bench

'None' (default) | 'ModelSim' | 'Incisive' | 'VCS' | 'Vivado Simulator'

When you set this property, the code generator generates a direct programming interface (DPI) component for your entire Simulink model, including your DUT and data sources. Your entire model must support C code generation with Simulink Coder™. The code generator produces a SystemVerilog test bench that compares the output of the DPI component with the output of the HDL implementation of your DUT. The code generator also builds shared libraries and generates a simulation script for the simulator you select.

Consider using this option if the default HDL test bench takes a long time to generate or simulate. Generation of a DPI test bench is sometimes faster than the default version because it does not run a full Simulink simulation to create the test bench data. Simulation of a DPI test bench with a large data set is faster than the default version because it does not store the input or expected data in a separate file. For an example, see Generate a SystemVerilog DPI Test Bench.

To use this feature, you must have HDL Verifier™ and Simulink Coder licenses. To run the SystemVerilog testbench with generated VHDL code, you must have a mixed-language simulation license for your HDL simulator.

Limitations

This test bench is not supported when you generate HDL code for the top-level Simulink model. Your DUT subsystem must meet the following conditions:

• Input and output data types of the DUT cannot be larger than 64 bits.

• Input and output ports of the DUT cannot use enumerated data types.

• Input and output ports cannot be single-precision or double-precision data types.

• The DUT cannot have multiple clocks. You must set the Clock inputs code generation option to Single.

• Use trigger signal as clock must not be selected.

• If the DUT uses vector ports, you must use Scalarize ports to flatten the interface.

• If the DUT uses non-virtual ports and Target language is VHDL or SystemVerilog, you must not select Preserve Bus structure in the generated HDL code.

See also SystemVerilog DPI test bench.

GenerateCoSimBlock — Generate HDL Cosimulation block

'off' (default) | 'on'

Generate an HDL Cosimulation block so you can simulate the DUT in Simulink with an HDL simulator.

For more information, see Cosimulation model.

GenerateCoSimModel — Generate HDL Cosimulation model

'ModelSim' (default) | 'Incisive' | 'VCS' | 'Vivado Simulator' | 'None'

Generate a model containing an HDL Cosimulation block for the specified HDL simulator.

For more information, see Cosimulation model.

Clock and Reset Input Options

ForceClock — Force clock input

'on' (default) | 'off'

Specify that the generated test bench drives the clock enable input based on ClockLowTime and ClockHighTime.

For more information, see Force clock.

ClockHighTime — Clock high time

5 (default) | positive integer

Clock high time during a clock period, specified in nanoseconds.

For more information, see Clock high time (ns).

ClockLowTime — Clock low time

5 (default) | positive integer

Clock low time during a clock period, specified in nanoseconds.

For more information, see Clock low time (ns).

ForceClockEnable — Force clock enable input

'on' (default) | 'off'

Specify that the generated test bench drives the clock enable input.

For more information, see Force clock enable.

TestBenchClockEnableDelay — Clock cycles between reset and clock enable

1 (default) | positive integer

Number of clock cycles between deassertion of reset and assertion of clock enable, specified as a positive integer.

For more information, see Clock enable delay (in clock cycles)

ForceReset — Force reset input

'on' (default) | 'off'

Specify that the generated test bench drives the reset input.

For more information, see Force reset.

ResetLength — Reset asserted time length

2 (default) | integer greater than or equal to 0

Length of time that reset is asserted, specified as the number of clock cycles.

For more information, see Reset length (in clock cycles).

Testbench Stimulus and Response Parameters

HoldInputDataBetweenSamples — Hold valid data for signals

'on' (default) | 'off'

Hold valid data between samples for signals clocked at slower rate.

For more information, see Hold input data between samples.

HoldTime — Hold time for inputs and forced reset

2 (default) | positive integer

Hold time for inputs and forced reset, specified in nanoseconds.

For more information, see Hold time (ns).

IgnoreDataChecking — Time to wait after clock enable before checking output data

0 (default) | positive integer

Time after clock enable is asserted before starting output data checks, specified in number of samples.

For more information, see Ignore output data checking (number of samples).

InitializeTestBenchInputs — Initialize test bench inputs

'off' (default) | 'on'

Initialize test bench inputs to zero. For more information, see Initialize test bench inputs.

Testbench Configuration Parameters

TestBenchDataPostFix — Postfix for test bench data file name

'_data' (default) | character vector

Postfix for test bench data file name, specified as a character vector.

For more information, see Test bench data file name postfix.

TestBenchPostFix — Postfix for test bench name

'_tb' (default) | character vector

Postfix for test bench name, specified as a character vector.

For more information, see Test bench name postfix.

TestBenchReferencePostFix — Postfix for test bench reference signal

'_ref' (default) | character vector

Postfix for test bench reference signal name, specified as a character vector.

For more information, see Test bench reference postfix.

MultifileTestBench — Generate multiple testbench files

'off' (default) | 'on'

Divide generated test bench into helper functions, data, and HDL test bench files.

For more information, see Multi-file test bench.

UseFileIOInTestBench — Use file I/O to read/write test bench data

'on' (default) | 'off'

For more information, see Use file I/O to read/write test bench data.

Floating Point Tolerance Options

FPToleranceStrategy — Floating-point tolerance strategy

'relative' (default) | 'ulp'

Floating-point tolerance check based on relative error or ULP. For more information, see Floating point tolerance check based on.

FPToleranceValue — Floating-point tolerance strategy

'relative' (default) | 'ulp'

Floating-point tolerance value depending on the FPToleranceStrategy specified. For more information, see Tolerance Value.

Port Names and Types

ClockInputs — Single or multiple clock inputs

'Single' (default) | 'Multiple'

Specify whether to generate single or multiple clock inputs in the HDL code. For more information, see Clock inputs.

ResetAssertedLevel — Asserted (active) level of reset

'active-high' (default) | 'active-low'

Specify whether to use an active-high or active-low asserted level for the reset input signal. For more information, see Reset asserted level.

ClockEnableInputPort — Clock enable input port name

'clk_enable' (default) | character vector

Specify the clock enable input port name as a character vector. For more information, see Clock enable input port.

ClockEnableOutputPort — Clock enable output port name

'ce_out' (default) | character vector

Clock enable output port name, specified as a character vector.

For more information, see Clock enable output port.

ClockInputPort — Clock input port name

'clk' (default) | character vector

Specify the clock input port name as a character vector. For more information, see Clock input port.

ResetInputPort — Reset input port name

'reset' (default) | character vector

Reset input port name, specified as a character vector.

For more information, see Reset input port.

File and Variable Names

VerilogFileExtension — Verilog file extension

'.v' (default) | character vector

Specify the file name extension for generated Verilog files. For more information, see Verilog file extension.

VHDLFileExtension — VHDL file extension

'.vhd' (default) | character vector

Specify the file name extension for generated VHDL files. For more information, see VHDL file extension.

VHDLArchitectureName — VHDL architecture name

'rtl' (default) | character vector

For more information, see VHDL architecture name.

VHDLLibraryName — VHDL library name

'work' (default) | character vector

For more information, see VHDL library name.

SplitEntityFilePostfix — Postfix for VHDL entity file names

'_entity' (default) | character vector

For more information, see Split entity file postfix.

SplitArchFilePostfix — Postfix for VHDL architecture file names

'_arch' (default) | character vector

For more information, see Split arch file postfix.

PackagePostfix — Postfix for package file name

'_pkg' (default) | character vector

Specify the postfix for the package file name as a character vector. For more information, see Package postfix.

ComplexImagPostfix — Postfix for imaginary part of complex signal

'_im' (default) | character vector

For more information, see Complex imaginary part postfix.

ComplexRealPostfix — Postfix for imaginary part of complex signal names

'_re' (default) | character vector

For more information, see Complex real part postfix.

EnablePrefix — Prefix for internal enable signals

'enb' (default) | character vector

Prefix for internal clock enable and control flow enable signals, specified as a character vector. For more information, see Clock enable input port and Enable prefix.

Coding Style

SplitEntityArch — Split VHDL entity and architecture into separate files

'off' (default) | 'on'

For more information, see Split entity and architecture.

UseVerilogTimescale — Generate 'timescale compiler directives

'on' (default) | 'off'

For more information, see Use Verilog or SystemVerilog `timescale directives.

DateComment — Include time stamp in header

'on' (default) | 'off'

For more information, see Emit time/date stamp in header.

InlineConfigurations — Include VHDL configurations

'on' (default) | 'off'

For more information, see Inline VHDL configuration.

ScalarizePorts — Flatten vector ports into scalar ports

'off' (default) | 'on' | 'dutlevel'

For more information, see Scalarize ports.

Script Generation

HDLCompileInit — Compilation script initialization text

'vlib %s\n' (default) | character vector

For more information, see Compile initialization.

HDLCompileTerm — Compilation script termination text

'' (default) | character vector

For more information, see Compile termination.

HDLCompileFilePostfix — Postfix for compilation script file name

'_compile.do' (default) | character vector

For more information, see Compile file postfix.

HDLCompileVerilogCmd — Verilog compilation command

'vlog %s %s\n' (default) | character vector

Verilog compilation command, specified as a character vector. The SimulatorFlags name-value pair specifies the first argument, and the module name specifies the second argument.

For more information, see Compile command for Verilog or SystemVerilog.

HDLCompileVHDLCmd — VHDL compilation command

'vcom %s %s\n' (default) | character vector

VHDL compilation command, specified as a character vector. The SimulatorFlags name-value pair specifies the first argument, and the entity name specifies the second argument.

For more information, see Compile command for VHDL.

HDLSimCmd — HDL simulation command

'vsim -voptargs=+acc %s.%s\n' (default) | character vector

The HDL simulation command, specified as a character vector.

For more information, see Simulation command.

HDLSimInit — HDL simulation script initialization name

['onbreak resume\n', 'onerror resume\n'] (default) | character vector

Initialization for the HDL simulation script, specified as a character vector.

For more information, see Simulation initialization.

HDLSimTerm — HDL simulation script termination name

'run -all' (default) | character vector

The termination name for the HDL simulation command, specified as a character vector.

For more information, see Simulation termination.

HDLSimFilePostfix — Postscript for HDL simulation script

'_sim.do' (default) | character vector

For more information, see Simulation file postfix.

HDLSimViewWaveCmd — HDL simulation waveform viewing command

'add wave sim:%s\n' (default) | character vector

Waveform viewing command, specified as a character vector. The implicit argument adds the signal paths for the DUT top-level input, output, and output reference signals.

For more information, see Simulation waveform viewing command.

Version History

Introduced in R2006b