addAXI4StreamInterface

R2026b

Class: hdlcoder.ReferenceDesign
Namespace: hdlcoder

Add AXI4-Stream interface

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Syntax

addAXI4StreamInterface(MasterChannelConnection=Master_Channel_Port,SlaveChannelConnection=Slave_Channel_Port)
addAXI4StreamInterface(MasterChannelConnection=Master_Channel_Port,SlaveChannelConnection=Slave_Channel_Port,Name=Value)

Description

addAXI4StreamInterface(MasterChannelConnection=Master_Channel_Port,SlaveChannelConnection=Slave_Channel_Port) adds an AXI4-Stream interface to an hdlcoder.ReferenceDesign object.

addAXI4StreamInterface(MasterChannelConnection=Master_Channel_Port,SlaveChannelConnection=Slave_Channel_Port,Name=Value) adds and defines an AXI4-Stream interface, with additional options specified by one or more name-value arguments.

Input Arguments

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Reference design port connected to the IP core AXI4-Stream master interface, specified as a character vector. This port must be an AXI4-Stream slave interface. If master_channel_enable is true, you must specify master_channel_port.

Example: 'axi_dma_0/S_AXIS_S2MM'

Reference design port connected to the IP core AXI4-Stream slave interface, specified as a character vector. This port must be an AXI4-Stream master interface. If slave_channel_number is true, you must specify slave_channel_port and slave_channel_data_width.

Example: 'axi_dma_0/M_AXIS_MM2S'

Tip

To add more than one AXI4-Stream interface to your reference design, call the addAXI4StreamInterface method multiple times depending on the number of interfaces that you want to add. For each additional interface, specify a unique InterfaceID.

Name-Value Arguments

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Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

Name of the AXI4-Stream interface that you add to the reference design, specified as a character vector. To create multiple AXI4-Stream interfaces, make sure that you use unique names for each interface.

Example: InterfaceID='AXI4-Stream1'

Master channel enable signal, specified as either true or false. By default, MasterChannelEnable is true, so you must specify master_channel_port. To use a reference design that has only a Slave channel, set MasterChannelEnable to false and do not specify the master_channel_port.

Example: MasterChannelEnable=false

Slave channel enable signal, specified as either true or false. By default, SlaveChannelEnable is true, so you must specify slave_channel_port. To use a reference design that has only a Master channel, set SlaveChannelEnable to false and do not specify the slave_channel_port.

Example: SlaveChannelEnable=false

Reference design master channel TDATA bit width, specified as a positive integer. By default, the master_channel_data_width is 32 bits.

Example: MasterChannelDataWidth=32

Reference design slave channel TDATA bit width, specified as a positive integer. By default, slave_channel_data_width is 32 bits.

Example: SlaveChannelDataWidth=32

Indicates if the AXI4-Stream interface is connected to the processor through a DMA. Set this value to true to enable device tree generation for the IP core AXI4-Stream interfaces.

Example: HasDMAConnection=true

Reference to the corresponding S2MM DMA node in the registered device tree. Set the value to match the name of the corresponding S2MM DMA node in the registered device tree. References to device tree nodes must start with "&". To reference a node by its label, specify "&" before the label, such as "&myLabel". To reference a node by its path, specify the path inside "&{" and "}", such as "&{/myNode/childNode}".

Set MasterChannelEnable to true to specify this value.

Example: DeviceTreeMasterChannelDMANode='&axi4stream_s2mm'

Reference to the corresponding MM2S DMA node in the registered device tree. Set the value to match the name of the corresponding MM2S DMA node in the registered device tree. References to device tree nodes must start with "&". To reference a node by its label, specify "&" before the label, such as "&myLabel". To reference a node by its path, specify the path inside "&{" and "}", such as "&{/myNode/childNode}".

Set SlaveChannelEnable to true to specify this value.

Example: DeviceTreeSlaveChannelDMANode='&axi4stream_m2ss'

Design fragment files to source into the generated Vivado® project, specified as a cell array. Use this argument to add hardware components that are required only when the AXI4-Stream interface is mapped, such as AXI DMA IP cores, AXI4-Stream infrastructure, or related interconnect logic.

Specify file names relative to the reference design plugin folder, as absolute paths, or relative to folders added by using addIncludeFolder. If the file is located in an added folder, you can specify only the file name.

This argument supports only Xilinx® Vivado reference designs. The design fragment files must use the .tcl extension. The generated project sources the specified files after the base custom block design TCL file and includes them only when the AXI4-Stream interface is mapped.

Example: DesignFragment={"shared\axi_stream_dma.tcl"} specifies a file name relative to the reference design plugin folder.

Example: DesignFragment={"C:\work\tcl\axi_stream_dma.tcl"} specifies an absolute file path.

Example: DesignFragment={"axi_stream_dma.tcl"} specifies a file in a folder added by using addIncludeFolder.

Device tree fragment files to append to the generated Linux® device tree, specified as a cell array. Use this argument to describe hardware resources associated with the AXI4-Stream interface, such as DMA channels and AXI4-Stream peripherals.

Specify file names relative to the reference design plugin folder, as absolute paths, or relative to folders added by using addIncludeFolder. If the file is located in an added folder, you can specify only the file name.

This argument supports only Xilinx Vivado reference designs. The device tree fragment files must use the .dts or .dtsi extension. The generated device tree appends the specified files and includes them only when the AXI4-Stream interface is mapped.

Example: DeviceTreeFragment={"shared\devicetree_axistream.dtsi"} specifies a file name relative to the reference design plugin folder.

Example: DeviceTreeFragment={"C:\work\devicetrees\devicetree_axistream.dtsi"} specifies an absolute file path.

Example: DeviceTreeFragment={"devicetree_axistream.dtsi"} specifies a file in a folder added by using addIncludeFolder.

Constraint files to add to the generated project, specified as a cell array. Use this argument to specify constraints associated with hardware introduced by the AXI4-Stream interface, such as pin assignments, I/O standards, clock constraints, or timing exceptions.

Specify file names relative to the reference design plugin folder, as absolute paths, or relative to folders added by using addIncludeFolder. If the file is located in an added folder, you can specify only the file name.

This argument supports only Xilinx Vivado reference designs. The constraint files must use the .xdc extension. The generated project adds the specified files to the project constraint set and includes them only when the AXI4-Stream interface is mapped.

Example: ConstraintFragment={"shared\led_peripheral.xdc"} specifies a file name relative to the reference design plugin folder.

Example: ConstraintFragment={"C:\work\constraints\led_peripheral.xdc"} specifies an absolute file path.

Example: ConstraintFragment={"led_peripheral.xdc"} specifies a file in a folder added by using addIncludeFolder.

Version History

Introduced in R2020a

See Also

Topics