Simple Dual Port RAM System
Simple Dual Port RAM block based on the hdl.RAM system object with ability to provide initial value
Libraries:
HDL Coder /
HDL RAMs
Description
The blocks are MATLAB System blocks that use the
hdl.RAM
System object™. You can specify the RAM type as Dual port
,
Simple dual port
, Single port
, True
dual port
, or Simple tri port
. In terms of simulation
behavior, the Dual Port RAM System block behaves similar to the
Dual Port RAM, the Single Port RAM System behaves
similar to the Single Port RAM, and so on. With the MATLAB
System blocks, you can:
Specify an initial value for the RAM. In the Block Parameters dialog box, enter a value for Initial output of RAM.
Obtain faster simulation results when you use these blocks in your Simulink® model.
Create parallel RAM banks when you use vector data by leveraging the
hdl.RAM
System object functionality.Obtain higher performance and support for large data memories.
Specify writable portions of bits in an addressed memory location by using column-write method. For more information, see Using the Column-Write Method to Selectively Write to Columns.
Limitations
When you build the FPGA bitstream for the RAM, the global reset logic does not reset the RAM contents. To reset the RAM, make sure that you implement the reset logic.
The RAM write address can be either
fixed-point (fi)
orinteger
, must be unsigned, and must be between2
and31
bits long.
Ports
Input
din — Write data input
scalar
| vector
Data to write into the RAM memory location when we
is true
, specified as a scalar or a vector. This
value can be double
, single
,
half
, integer
, or a
fixed-point (fi)
object, and can be real or
complex.
Bus Support:
You can use non-virtual bus and array of buses at the data port for HDL code generation.
Data Types: single
| double
| half
| int8
| int16
| uint8
| uint16
| Boolean
| fixed point
wr_addr — Write address
scalar
| vector
Address to write, specified as a scalar or a vector. The RAM address
where you write the data into. This value can be either
fixed-point (fi)
or integer
,
must be unsigned, and must be between 2
and
31
bits long.
Dependencies
To enable this port, set the Type of RAM
parameter to Simple dual port
or
Dual port
.
Data Types: uint8
| uint16
| fixed point
we — Write enable
scalar
| vector
Write enable, specified as a scalar or a vector. When
we
is true, the RAM writes the data into the
memory location that you specify. If you set the Type of
RAM parameter to Single port
,
the RAM reads the value in the memory location addr
when we
is false
. This value can
be either Boolean
, integer
, or
fixed-point (fi)
.
Note
To use column-write method the data type must be an
integer
or a fixed-point
(fi)
.
Data Types: uint8
| uint16
| uint32
| uint64
| Boolean
| fixed point
rd_addr — Read address
scalar
| vector
Address to read, specified as a scalar or a vector. The address to
read the data from the RAM. This value can be either
fixed-point (fi)
or integer
,
and must be real and unsigned.
Dependencies
To enable this port, set the Type of RAM
parameter to Simple dual port
or
Dual port
.
Data Types: uint8
| uint16
| fixed point
Output
dout — Read data
scalar
| vector
Old output data that the RAM reads from the memory location
rd_addr
.
Dependencies
To enable this port, set the Type of RAM
parameter to Simple dual port
.
Parameters
Main
Type of RAM — RAM type
Dual port
(default) | Simple dual port
| Single port
| True dual port
| Simple tri port
Type of RAM, specified as either:
Single port
— Create a single port RAM with Write data, Address, and Write enable as inputs and Read data as the output.Simple dual port
— Create a simple dual port RAM with Write data, Write address, Write enable, and Read address as inputs and data from read address as the output.Dual port
— Create a dual port RAM with Write data, Write address, Write enable, and Read address as inputs and data from read address and write address as the outputs.True dual port
— Create a true dual port RAM with Write dataa
andb
, Write/Read addressa
andb
, and Write enablea
andb
as inputs and data from write addressa
andb
as the outputs.Simple tri port
— Create a simple tri port RAM with Write data, Write address, Write enable, and Read addressa
andb
as inputs and data from read addressa
andb
as the outputs.
The code generator dynamically configures the input and output ports of the block based on the RAM type that you specify.
Use asynchronous read feature in target hardware — Use asynchronous read feature in target hardware
off
(default) | on
Use the asynchronous read feature in your target hardware, specified as a check box. Boards that support asynchronous read allow the hardware to execute a read instruction immediately instead of waiting one cycle.
Data Types: Boolean
Initial output of RAM — Initial simulation output of RAM
'0.0'
(default) | Scalar
| Vector
Initial simulation output of the System object, specified as either:
A scalar value.
A vector with one-to-one mapping between the initial value and the RAM words.
An n-by-m matrix with one-to-one mapping between the initial values and the RAM words in the RAM banks, where n represents the number of RAM banks and m represents the number of address location in the RAM block, or vice-versa.
Advanced
Model RAM with cycle of delay — Model RAM with one cycle of delay
on
(default) | off
Since R2024b
If you specify:
true
The RAM delays the input data by one cycle before the output can read it.
The RAM is cycle-accurate to the generated HDL code.
false
The RAM reads and outputs the input data immediately, but adds one cycle of latency during HDL code generation.
You can leverage clock-rate pipelining when you specify an oversampling value or work with multirate models.
Dependencies
To enable this property, clear the Use asynchronous read feature in target hardware parameter.
Programmatic Use
Block Parameter: ModelRAMDelay |
Type: character vector, string |
Values: "on" | "off" |
Default: "on" |
Data Types: Boolean
More About
Using the Column-Write Method to Selectively Write to Columns
You can use the column-write method to view the RAM as a collection of equally sized columns. During a write cycle, you can write into each of these columns separately. The data type and value of the write enable input, along with the data type of write data input, determine the size of each column and the columns in which the block writes in the addressed memory location.
In this context:
DT is the data type of the write data input signal
din
.DW is the data width of the input data, which is equal to word length of the
din
value.DTWE is the data type of the write enable signal
we
. This signal determines which columns the block writes in the addressed memory location. The block writes the columns based on the position of the 1s in the binary representation of the value ofwe
.NC is the number of columns which you can partition the RAM space to write the data, which is equal to word length of
we
value.WC is the width of each column, which is equal to DW divided by NC.
The table summarizes the relationship among the data types of the write data input, the data types of write enable input, the number of columns, and the width of each column.
DT | DW | DTWE | NC | WC in Bits |
---|---|---|---|---|
uint16 | 16 | ufix4 | 4 | 4 |
uint32 | 32 | ufix4 | 4 | 8 |
uint64 | 64 | ufix4 | 4 | 16 |
uint32 | 32 | uint8 | 8 | 4 |
uint64 | 64 | uint8 | 8 | 8 |
int32 | 32 | uint16 | 16 | 2 |
For example, if DT is uint16
and
WE is ufix4
, then DW is
equal to 16, NC is equal to 4, and WC is equal
to 4 bits. If the input to din
is 980
, its
binary representation is 0000001111010100
. The column-wise
representation of din
is c4 = 0000
, c3 =
0011
, c2 = 1101
, and c1 =
0100
, where c1 is the first column.
The table summarizes the results of using the column-write method for different input combinations.
Value of we | Binary Representation of
we | Columns Selected for Writing in RAM | Data at Memory Location | dout | |
---|---|---|---|---|---|
Before Performing Write Operation | After Performing Write Operation | ||||
3 | 0011 | c2, c1 | c4 = c3 =
c2 =
c1 =
| c4 = c3 =
c2 =
c1 =
| 212 |
4 | 0100 | c3 | c4 = c3 =
c2 =
c1 =
| c4 = c3 =
c2 = c1 =
| 768 |
6 | 0110 | c3, c2 | c4 = c3 =
c2 =
c1 =
| c4 = c3 =
c2 =
c1 =
| 976 |
9 | 1001 | c4, c1 | c4 = c3 =
c2 =
c1 =
| c4 = c3 =
c2 =
c1 =
| 4 |
9 | 1001 | c4, c1 | c4 = c3 =
c2 =
c1 =
| c4 = c3 =
c2 =
c1 =
| 4084 |
Inputs with signed data types and with non-zero fraction lengths are not supported by the write enable input port.
The word length of the write data input must a multiple of the word length of the write enable.
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
The block has a MATLABSystem
architecture which
indicates that the block implementation uses the hdl.RAM
System object.
General | |
---|---|
ConstrainedOutputPipeline | Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
|
InputPipeline | Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
OutputPipeline | Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
RAMDirective | Specify whether to map RAM blocks in your design to RAM
blocks on the target FPGA. For UltraRAM mapping,
Initial output of RAM must
be set to |
This block supports code generation for complex signals.
The block does not support:
Nested bus at the data port.
Non-zero values at the Initial output of RAM when using non-virtual bus input to the data port.
Version History
Introduced in R2017bR2024b: Use clock-rate pipelining
You can use Simple Dual Port RAM System block inside a data rate feedback loop and use clock-rate pipelining optimization. This model design is helpful for applications that require programmable or tunable lookup tables without having to regenerate bitstreams.
Use the new parameter Model RAM with cycle of delay to model delay in your simulation. Model RAM with cycle of delay is enabled by default and is disabled when Use asynchronous read feature in target hardware is enabled.
R2024b: Parameter name changes
These parameters are renamed:
Previous Name | Current Name |
---|---|
Specify the type of RAM | Type of RAM |
Enable asynchronous reads | Use asynchronous read feature in target hardware |
Specify the RAM initial value | Initial output of RAM |
R2024b: Write to RAM in columns using column-write operations in RAM System blocks
In this block, you can use the column-write method to selectively modify specific parts of the memory without altering the remaining parts at a specified memory address.
R2024b: Initialize RAM banks with unique initial values for vector data inputs
In this block, you can initialize RAM banks with unique initial values.
R2024a: Array of Buses Input Support
The block now supports HDL code generation for input data specified as an array of buses.
R2024a: Half-Precision and Boolean Data Support
The block now supports HDL code generation with input data of type
Half
or
Boolean
.
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