Treat Simulink rates as actual hardware rates

R2026b

Set oversampling value based on model rates and target frequency values

Since R2023b

Model Configuration Pane: Global Settings

Description

Use this parameter to let HDL Coder™ automatically set an oversampling value based on your Simulink® model rates and the Target Frequency (MHz) parameter value during HDL code generation.

When you select this parameter, you can make changes to your design data and clock rates without manually calculating and updating the oversampling value. For example, select this parameter if you have complex feedback loops with multiple optimizations enabled for your model and you want the fastest data rate possible while allowing the optimizations to perform.

Dependencies

You must set the Target Frequency (MHz) parameter to a target clock rate greater than 0 to select Treat Simulink rates as actual hardware rates.

Settings

off (default) | on

Default: Off

on

Treat Simulink rates as actual hardware rates and let HDL Coder set an oversampling value automatically. Express your data rate in terms of Simulink model rates and clock rate in terms of the Target Frequency (MHz) parameter. HDL Coder automatically sets an oversampling value based on your data and clock rates during HDL code generation. When you select Treat Simulink rates as actual hardware rates, you cannot change the Oversampling factor parameter.

off

Do not treat Simulink rates as actual hardware rates. You can use the Oversampling factor parameter to manually specify the oversampling value.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can use the TreatRatesAsHardwareRates setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model by using either of these methods:

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
        'TreatRatesAsHardwareRates','on')

  • Enable the parameter on the model by using hdlset_param, and then generate HDL code by using makehdl.

    hdlset_param('sfir_fixed','TreatRatesAsHardwareRates','on')
makehdl('sfir_fixed/symmetric_fir')

Recommended Settings

No recommended settings.

Programmatic Use

Parameter: TreatRatesAsHardwareRates
Type: character vector
Value: 'on' | 'off'
Default: 'off'

Limitations

When you use the Treat Simulink rates as actual hardware rates parameter, HDL Coder computes the oversampling factor as the ratio of the Target Frequency parameter value to the DUT base sample rate. The target frequency must be an integer multiple of the DUT base rate. Otherwise, HDL Coder cannot derive a valid oversampling factor and might instead generate a clock that depends on other HDL Coder optimizations. Choose a target frequency that is an integer multiple of the DUT base rate. For example, for a 48 kHz base rate, valid target frequencies include 48 MHz, 96 MHz, and 192 MHz.

When HDL Coder cannot derive a valid oversampling factor:

  • HDL Coder does not use the target frequency to determine the generated clock rate.

  • HDL Coder generates a clock that defaults to the minimum oversampling required by other HDL Coder optimizations, such as resource sharing or streaming.

  • HDL Coder might generate HDL code that operates at a clock frequency lower than the specified target frequency.

For example, consider a model with a DUT base rate of 48 kHz and a target frequency of 50 MHz. The ratio between the target frequency and the DUT base sample rate is 50,000,000 / 48,000 = 1041.67, which is not an integer. HDL Coder generates a 48 kHz clock.

Next, suppose the example model uses the resource sharing optimization in HDL Coder. The DUT has the SharingFactor HDL block property set to 100. Because the ratio between the target frequency and the DUT base sample rate is not an integer, HDL Coder generates a clock at 100 x 48,000 = 4.8 MHz instead of the requested 50 MHz.

Version History

Introduced in R2023b

See Also

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