Clock-Rate Pipelining

Clock-rate pipelining is an optimization framework in HDL Coder™ that allows other speed and area optimizations to introduce latency at the clock rate. When modeling at a rate slower than the clock rate, clock-rate pipelining automatically upsamples these slower regions such that the latency introduced by other optimizations is either minimized or offset by data rate delay. Clock-rate pipelining does not attempt to optimize a design without other speed and area optimization requests. You can use clock-rate pipelining with a Simulink^® model or a MATLAB^® function.

Rationale for Clock-Rate Pipelining

HDL Coder introduces pipelines when you specify certain block implementations or enable some optimizations on the Simulink model or MATLAB function, such as:

Multi-cycle block implementations
Input and output pipelining
Distributed pipelining (includes setting the HDL block property ConstrainedOutputPipeline)
Adaptive pipelining
Floating-point library mapping
Native floating-point HDL code generation
Resource sharing
Streaming
Mapping of lookup table (LUT) to RAM
Blocks which add latency during code generation automatically (For example, Product, Divide, and Math Function blocks with HDL architecture set to ShiftAdd, Sqrt)

By default, in slow paths, these pipeline registers operate at the slow data rate. When you enable clock-rate pipelining, the pipeline registers operate at the faster clock rate. Clock-rate pipelining does not affect existing design delays in your model. It is an alternative to using multicycle path constraints with your synthesis tool.

How Clock-Rate Pipelining Works in a Simulink Model

The clock-rate pipelining optimization identifies slow paths or regions in the model by analyzing the block sample times. Blocks that have a sample time greater than the device under test (DUT) base sample time are part of the slow path, and are potential candidates for clock-rate pipelining. In these slow paths, HDL Coder enables optimizations to introduce pipeline delays at the clock rate.

If you set the Oversampling factor configuration parameter to a value greater than 1 or you enable the Treat Simulink rates as actual hardware rates configuration parameter, the DUT sample time becomes slower than the actual clock rate. HDL Coder determines the maximum number of clock-rate pipelines that it can insert based on the DUT-to-block sample time ratio and the oversampling value:

Maximum number of clock-rate delays = (block_rate ÷ DUT_base_rate) × Oversampling

If you are modeling with actual hardware rates, enable the Treat Simulink rates as actual hardware rates parameter to set an oversampling value for your model automatically. If you are modeling with relative rates in Simulink, set the Oversampling factor parameter to a value greater than 1 to set an oversampling value for your model. When you enable the Treat Simulink rates as actual hardware rates parameter, HDL Coder can automatically adjust the oversampling value for your model if changes in Simulink rate or target frequency occur, without requiring you to update the Oversampling factor manually.

Clock-rate pipelining identifies regions in the model that have the same slow data rate and are delimited by either Delay blocks or blocks that introduce a rate transition. HDL Coder converts these regions to the faster clock rate by introducing Repeat blocks at the input of the region and Rate Transition blocks at the output of the region. If the output of a clock-rate region is a Delay block at the data rate, HDL Coder absorbs that Delay block. To accommodate the delay, HDL Coder introduces several clock-rate pipelines that correspond to the ratio of the data rate to the clock rate.

How Clock-Rate Pipelining Works in a MATLAB Function

A MATLAB function, which is the DUT when generating HDL code from MATLAB, runs at a single data rate. If you want a clock rate that is faster than the data rate, you can use clock-rate pipelining. You specify how much faster you want your clock rate to be than the DUT data rate by specifying an oversampling factor greater than one. The maximum number of clock-rate delays that HDL Coder can insert is equal to the oversampling factor.

You can also use clock-rate pipelining to optimize speed if you have other code generation options that introduce latency in a feedback loop, such as the use of persistent variables or native floating point.

Clock-Rate Pipelining and Hierarchy Flattening

You can use the clock-rate pipelining optimization with or without flattening the subsystem hierarchy. Flatten the subsystem hierarchy when you want to maximize opportunities for sharing resources in your design. To flatten the subsystem hierarchy, enable FlattenHierarchy on the top-level Subsystem. By default, all Subsystem blocks inside the top-level subsystem inherit this FlattenHierarchy setting. Hierarchy flattening brings several clock-rate regions to the same level in the hierarchy and combines them, which increases opportunities for clock-rate pipelining. However, it breaks the modularity of your design and affects the readability of the generated HDL code. See also Hierarchy Flattening.

To apply clock-rate pipelining without flattening the hierarchy, on the top-level subsystem in your model, disable FlattenHierarchy. If your design uses fixed-point data types, enable some optimizations on the underlying subsystems. In this case, HDL Coder introduces clock-rate pipelines in your design while preserving the subsystem hierarchy, which:

Improves the modularity of your design and makes navigation through the generated model easier especially in large designs with complex hierarchies.
Improves readability of the generated HDL code by creating multiple Verilog, SystemVerilog or VHDL files for the various Subsystem blocks in your design.

Clock-Rate Pipelining for DUT Output Ports

To produce DUT outputs as soon as possible by passing the outputs from the DUT at the clock rate rather than the data rate, select the Allow clock-rate pipelining of DUT output ports configuration parameter or use the ClockRatePipelineOutputPorts property. This property changes the timing of your DUT interface by changing the sample time of the DUT output ports from a slower data rate to the clock rate. To adjust for the difference in timing, HDL Coder generates messages that provide the phase offset of each output port. For example, this message means that the output data from portname is valid after 31 clock cycles: Phase of output port portname: 31 clock cycles. To set this parameter, see Allow clock-rate pipelining of DUT output ports.

The validation model adjusts for the timing difference by inserting a Rate Transition block at the DUT output and comparing the output of the Rate Transition block with the original output. The RTL test bench logs the output data at the input of the Rate Transition block and compares it with the DUT output in the RTL simulation.

When producing DUT outputs at the clock rate, the outputs are ready as soon as possible, even if one output is ready before another. For example, this is useful if you run a hardware-in-the-loop simulation with a control system and have a plant model running at a slow rate and discrete logic such as control signals in the DUT that need to run at a faster rate or with a short response delay time. To synchronize the outputs while still satisfying the highest-latency requirements of the outputs, you can balance clock-rate pipelined DUT output ports by selecting the Balance clock-rate pipelined DUT output ports configuration parameter or using the BalanceClockRateOutputPorts property. You can apply this property when interfacing your logic with a valid signal interface to align the output of your logic path and the output of the valid signal path. To set this parameter, see Balance clock-rate pipelined DUT output ports.

Specify Clock-Rate Pipelining

You can generate HDL code with the clock-rate pipelining optimization from a Simulink model or MATLAB function.

Specify Clock-Rate Pipelining for a Simulink Model

You can set clock-rate pipelining on a model or, for finer control, on subsystems within the top-level DUT subsystem. By default, clock-rate pipelining is enabled on the model. To disable clock-rate pipelining from the UI:

In the Apps tab, select HDL Coder. The HDL Code tab appears.
Click Settings. In the HDL Code Generation > Optimization > Pipelining tab, clear Clock-rate pipelining and click OK.

At the command line, use the makehdl or hdlset_param function to set the ClockRatePipelining property to off.

You can use clock-rate pipelining for a subsystem within the top-level DUT subsystem. To model a control path in your design at the data rate instead of the clock rate, put the control path in a subsystem, and disable clock-rate pipelining for that subsystem. To disable clock-rate pipelining for a subsystem within the top-level DUT subsystem, set ClockRatePipelining to off for that subsystem. See also Set Clock-Rate Pipelining For a Subsystem.

Specify Clock-Rate Pipelining for a MATLAB Function

To enable the clock-rate pipelining for a MATLAB function:

Open the MATLAB HDL Workflow Advisor. To get started with the MATLAB HDL Workflow Advisor, see Basic HDL Code Generation and FPGA Synthesis from MATLAB.
In the left pane, click the HDL Code Generation task. In the right pane, navigate to the Optimization tab and select Clock Rate Pipelining.
Click the Clocks & Ports tab and set Oversampling factor to a value greater than one.

Clock-Rate Pipelining Report

To see the clock-rate pipelining information in the report, before you generate code for each subsystem or model reference, enable the optimization report. In theHDL Code Generation > Report section of the Configuration Parameters dialog box, select Generate optimization report.

When you generate the optimization report, you can use the Clock-Rate Pipelining section of the report to see how the clock-rate pipelining optimization performed in your model. The Clock-Rate Pipelining section includes:

Whether clock-rate pipelining and its associated optimizations ran in the model successfully
The oversampling factor used in the model
The clock rate used for clock-rate pipelining
A list of the clock-rate pipelining obstacles and a link that highlights the obstacles in the original and generated models
The suggested oversampling factor, if possible
Latency budgets for loops, if possible

For more information on how to create and use the code generation report, see Create and Use Code Generation Reports.

Limitations for Clock-Rate Pipelining

These blocks do not support clock-rate pipelining, and therefore delimit clock-rate pipelining regions:

Deserializer1D
Serializer1D
HDL FIFO
HDL Cosimulation
Hit Crossing
MATLAB System, if it uses persistent variables
Reusable Subsystem (CodeReuseSubsystem), if FlattenHierarchy is not enabled
Model. Use a Subsystem Reference instead.

HDL Coder does not support clock-rate pipelining for:

Subsystem or Model block with HDLArchitecture set to BlackBox.
Black box subsystem or black box model reference blocks.
Subsystems that contain blocks not supported for clock-rate pipelining.
DSP Builder for Intel^® FPGAs subsystems.
System Generator for DSP subsystems.
Communications Toolbox™ blocks.
Wireless HDL Toolbox™ blocks.
Vision HDL Toolbox™ blocks.

HDL Coder does not support applying both the streaming and sharing optimizations on the same resource when you use the clock-rate pipelining optimization. Either disable clock-rate pipelining or use either the streaming optimization or the sharing optimization on the same resource when clock-rate pipelining is enabled.

HDL Coder does not support clock-rate pipelining when Clock inputs is set to Multiple.