Custom IP Core Generation
Using the HDL Workflow Advisor, you can generate a custom IP core from a model or algorithm. The generated IP core is sharable and reusable. You can integrate it with a larger design by adding it in an embedded system integration environment, such as Intel® Qsys, Xilinx® EDK, or Xilinx IP Integrator.
To learn how to generate a custom IP core, see:
Custom IP Core Architectures
You can generate an IP core:
With an AXI4 or AXI4-Lite interface.
With an AXI4 or AXI4-Lite interface and AXI4-Stream Video interfaces.
Without any AXI4 or AXI4-Lite interfaces. To learn more, see Generate Board-Independent HDL IP Core from Simulink Model.
The Algorithm from MATLAB and Simulink block represents your DUT. HDL Coder™ generates the rest of the IP core based on your target platform interface settings and processor or FPGA synchronization mode.
Target Platform Interfaces
You can map each port in your DUT to one of these target platform interfaces in the IP core:
AXI4-Lite: Use this interface to access control registers or for lightweight data transfer. HDL Coder generates memory-mapped registers and allocates address offsets for the ports. See Model Design for AXI4 Slave Interface Generation.
AXI4: Use this interface to connect to components that support burst data transmission. HDL Coder generates memory-mapped registers and allocates address offsets for the ports. In the generated HDL IP core, you can have either AXI4 or AXI4-Lite interface but not both interfaces. See Model Design for AXI4 Slave Interface Generation.
AXI4-Master: Use this interface for designs that require accessing large data sets from an external memory. For more information, see Model Design for AXI4 Master Interface Generation.
AXI4-stream: Use this interface for designs that require high speed data transfers. See Model Design for AXI4-Stream Interface Generation.
AXI4-Stream Video: Use this interface to send or receive a 32-bit scalar video data stream. See Model Design for AXI4-Stream Video Interface Generation.
External ports: Use external ports to connect to FPGA external IO pins or to other IP cores with external ports.
FPGA Data Capture: Use FPGA Data Capture over the JTAG or Ethernet interface to observe test point signals and signals at the DUT output ports while your design runs on the FPGA. For an example of marking internal signals as test points, see Debug IP Core Using FPGA Data Capture. For more information on capturing data, see Data Capture Workflow (HDL Verifier).
To use this interface, you must download a hardware support package for your FPGA board. See Download FPGA Board Support Package (HDL Verifier).
To learn more about the AXI4, AXI4-Lite, and AXI4-Stream Video protocols, refer to your target hardware documentation. To add multiple AXI4-Stream and AXI4-Master interfaces and generate an IP core with multiple interfaces, see Generate HDL IP Core with Multiple AXI4-Stream and AXI4 Master Interfaces.
Processor and FPGA Synchronization
HDL Coder generates synchronization logic in the IP core based on the processor and FPGA synchronization mode that you choose.
When generating a custom IP core, these processor and FPGA synchronization options are available:
Coprocessing – blocking
To learn more, see Processor and FPGA Synchronization.
Custom IP Core Generated Files
After you generate a custom IP core, the IP core files are in the
ipcore folder within your project folder. In the HDL Workflow
Advisor, you can view the IP core folder name in the IP core folder
field of the HDL Code Generation > Generate RTL Code and IP Core task.
The IP core folder contains:
IP core definition files.
HDL source files (
A C header file with the register address map.
(Optional) An HTML report with instructions for using the core and integrating the IP core in your embedded system project.
When you use the multicycle path constraints to meet the timing requirements, HDL Coder generates the constraints file of XDC format (
.xdc) for Xilinx workflow and SDC format (
.sdc) for Intel workflow.
The IP Core Generation workflow does not support :
RAM Architecture set to
Generic RAM without clock enable.
Using different clocks for the IP core and the AXI interface. The
AXILite_ACLKmust be synchronous and connected to the same clock source. The
AXILite_ARESETNmust be connected to the same reset source. See Synchronization of Global Reset Signal to IP Core Clock Domain.
- Access DUT Registers on Xilinx Pure FPGA Board Using IP Core Generation Workflow
- Access DUT Registers on Intel Pure FPGA Board Using IP Core Generation Workflow