Use the FPGA data capture feature to observe signals from your design while the design is running on the FPGA. This feature captures a window of signal data from the FPGA and returns the data to MATLAB® or Simulink® over a JTAG or Ethernet interface.
FPGA data capture support for JTAG connections is available for Intel® and Xilinx® FPGA boards. Support for Ethernet connections is available for Xilinx FPGA boards only.
To use this feature, you must download a hardware support package for your FPGA board. See Download FPGA Board Support Package.
You can choose between two workflows to capture data from your FPGA board and return it to MATLAB or Simulink.
First workflow — If you generate the HDL IP with HDL Coder™, use the HDL Workflow Advisor tool to generate the data capture IP and integrate it into your FPGA design.
Second workflow — If you have an existing HDL design, use HDL Verifier™ tools to generate the data capture IP. Then, manually integrate the generated IP into your FPGA design.
To capture data over a JTAG interface, you can follow either of these workflows. To capture data over an Ethernet interface, you must follow the second workflow.
To capture signals from your design, HDL Verifier generates an IP core that communicates with MATLAB. Use the HDL Coder workflow to automatically integrate the data capture IP core in your design. Otherwise, manually integrate this IP core into your HDL project and deploy it to the FPGA along with the rest of your design. Then, use one of these methods to capture data.
For capturing data to MATLAB – HDL Verifier generates a customized app that returns the captured signal data. Alternatively, you can use the generated System object™ to capture data programmatically.
For capturing data to Simulink – HDL Verifier generates a block that has output ports corresponding to the signals you captured.
In both cases, you can specify data types for the captured data, number of windows to capture, and trigger conditions that control when the data is sampled.
When the design is running on the FPGA, first the generated IP core waits for the trigger condition that you specify. Define a trigger condition by specifying values matched on one or more signals. When the trigger is detected, the logic captures the designated signals to a buffer and returns the data over the JTAG or Ethernet interface to the host machine. You can then analyze and display these signals in your MATLAB workspace or Simulink model.
When you use HDL Workflow Advisor tool to generate your HDL design, first mark desired signals as Configure Signals as Test Points (Simulink) in Simulink. Configure your design using HDL Workflow Advisor tool to:
Enable test point generation by selecting the Enable HDL DUT port generation for test points option in the Set Target Interface step. For more information, see Set Target Interface (HDL Coder).
Connect test point signals to the FPGA Data Capture - JTAG interface in the Set Target Interface step.
Set up the buffer size and maximum sequence depth for data collection in the Generate RTL Code and IP Core step. For more information, see Generate RTL Code and IP Core (HDL Coder).
Then, execute the remaining steps to generate HDL for your design and program the FPGA. The data capture IP core is integrated into the generated FPGA design. You can now Capture Data from the FPGA.
For an example of using data capture with HDL Workflow Advisor, see Debug IP Core Using FPGA Data Capture (HDL Coder).
Before capturing FPGA data, you must first specify which signals to capture and how many data samples to return. When using an existing HDL design, use the FPGA Data Capture Component Generator tool to configure settings and generate the data capture IP core. The IP core contains:
A port for each signal you want to capture or use as part of a trigger condition
Memory to capture the number of samples you requested for each signal
JTAG or Ethernet interface logic to communicate with MATLAB
Trigger logic that can be configured at run time
The FPGA Data Capture Component Generator tool also generates a customized FPGA Data Capture tool, System object, and model that communicate with the FPGA.
For MATLAB to communicate with the FPGA, you must integrate the generated HDL IP core into your FPGA design. If you used the HDL Workflow Advisor tool to generate your data capture IP, this step is automated. In this case, data capture IP operates on a single-clock rate, which is the primary clock of your design under test (DUT). If you did not use the HDL Workflow Advisor tool, follow these instructions in the generation report.
Create an FPGA project.
Navigate to the
Follow one of these steps based on your connection type.
JTAG — Add the generated HDL files in the
hdlsrc folder into your FPGA
project. Then, instantiate the HDL IP core,
datacapture, in your HDL code.
datacapture to the signals
you requested for capture and triggers.
Ethernet — Run the
insertEthernet.tcl script in the
Vivado® Tcl console by entering the
Compile the project and program the FPGA with the new image via a JTAG cable. You can now Capture Data from the FPGA.
The FPGA data capture IP core communicates over the JTAG or Ethernet cable between your FPGA board and the host computer. Make sure that the required cable is connected. Before capturing data, you can set data types for the captured data, and set trigger conditions that specify when to capture the data. To configure these options and capture data, you can:
Open the FPGA Data Capture tool. Set trigger and data type parameters, and then capture data into the MATLAB workspace.
Use the generated System object derived from
hdlverifier.FPGADataReader. Set the data types and
trigger condition using the methods and properties of the
System object, and then call the object to capture data.
In Simulink, open the generated model, and configure the parameters of the FPGA Data Reader block. Then, run the model to capture data.
After you capture the data into the MATLAB workspace or Simulink model, you can analyze, verify, and display the data.