Implement rSqrt Block with Control Signals
This example shows how to implement the control-signal based reciprocal square root block and use it to generate HDL code.
Open and Run Simulink Model
Specify the input data as a linear sweep. You can change these values according to your requirements.
RSQRT_input = fi(1/10:1/10:100,0,16,8)';
Specify the word length for fixed-point datatypes and the latency for the model.
WL = 16; latency = 17;
Open the hdlcoder_rsqrt_bitset_control
model and specify a stop time sufficient to process all the input combinations.
stoptime = length(RSQRT_input)-1+latency; open_system('hdlcoder_rsqrt_bitset_control') sim('hdlcoder_rsqrt_bitset_control')
This figure shows the simulation waveform for the model. You can see that dataOut
output is valid when validOut
is 1
.
Validate Simulink Output by Using Reference Output
To validate the output of the Simulink model, compare this output to a reference value. Compute the reference output by using the 1/|sqrt| operation.
ref_RSQRT = sqrt(1./double(RSQRT_input));
Use logical indexing to extract valid output.
implementation_RSQRT = simulink_RSQRT(valid_output);
Plot the comparison results by using the comparison_plot_rsqrt
function. The maximum error value is significantly smaller than the output of the model.
comparison_plot_rsqrt(ref_RSQRT,implementation_RSQRT,1,'rSQRT linear input');
Maximum Error rSQRT linear input 3.906250e-03 Maximum PctError rSQRT linear input 3.819748e+00
Generate HDL Code for Reciprocal Square Root Implementation
Check the HDL settings of the model by using the hdlsaveparams
function.
hdlsaveparams('hdlcoder_rsqrt_bitset_control')
%% Set Model 'hdlcoder_rsqrt_bitset_control' HDL parameters hdlset_param('hdlcoder_rsqrt_bitset_control', 'Backannotation', 'on'); hdlset_param('hdlcoder_rsqrt_bitset_control', 'HDLSubsystem', 'hdlcoder_rsqrt_bitset_control'); hdlset_param('hdlcoder_rsqrt_bitset_control', 'ResetType', 'Synchronous'); hdlset_param('hdlcoder_rsqrt_bitset_control', 'SynthesisTool', 'Xilinx Vivado'); hdlset_param('hdlcoder_rsqrt_bitset_control', 'SynthesisToolChipFamily', 'Virtex7'); hdlset_param('hdlcoder_rsqrt_bitset_control', 'SynthesisToolDeviceName', 'xc7v2000t'); hdlset_param('hdlcoder_rsqrt_bitset_control', 'SynthesisToolPackageName', 'fhg1761'); hdlset_param('hdlcoder_rsqrt_bitset_control', 'SynthesisToolSpeedValue', '-2'); hdlset_param('hdlcoder_rsqrt_bitset_control', 'TargetDirectory', 'hdl_prj\hdlsrc'); hdlset_param('hdlcoder_rsqrt_bitset_control', 'TargetFrequency', 500); hdlset_param('hdlcoder_rsqrt_bitset_control', 'Traceability', 'on'); % Set SubSystem HDL parameters hdlset_param('hdlcoder_rsqrt_bitset_control/rSqrt', 'FlattenHierarchy', 'on'); hdlset_param('hdlcoder_rsqrt_bitset_control/rSqrt/LumpLatency', 'Architecture', 'MATLAB Datapath'); % Set SubSystem HDL parameters hdlset_param('hdlcoder_rsqrt_bitset_control/rSqrt/LumpLatency', 'FlattenHierarchy', 'on'); hdlset_param('hdlcoder_rsqrt_bitset_control/rSqrt/ValidLine', 'Architecture', 'MATLAB Datapath'); % Set SubSystem HDL parameters hdlset_param('hdlcoder_rsqrt_bitset_control/rSqrt/ValidLine', 'FlattenHierarchy', 'on'); hdlset_param('hdlcoder_rsqrt_bitset_control/rSqrt/rSqrt', 'Architecture', 'RecipSqrtNewtonSingleRate');
To generate HDL code for the rSqrt block in the model, use the makehdl
function.
makehdl('hdlcoder_rsqrt_bitset_control/rSqrt') close_system('hdlcoder_rsqrt_bitset_control') close all;
### Working on the model <a href="matlab:open_system('hdlcoder_rsqrt_bitset_control')">hdlcoder_rsqrt_bitset_control</a> ### Generating HDL for <a href="matlab:open_system('hdlcoder_rsqrt_bitset_control/rSqrt')">hdlcoder_rsqrt_bitset_control/rSqrt</a> ### Using the config set for model <a href="matlab:configset.showParameterGroup('hdlcoder_rsqrt_bitset_control', { 'HDL Code Generation' } )">hdlcoder_rsqrt_bitset_control</a> for HDL code generation parameters. ### Running HDL checks on the model 'hdlcoder_rsqrt_bitset_control'. ### Begin compilation of the model 'hdlcoder_rsqrt_bitset_control'... ### Begin compilation of the model 'hdlcoder_rsqrt_bitset_control'... ### Working on the model 'hdlcoder_rsqrt_bitset_control'... ### Working on... <a href="matlab:configset.internal.open('hdlcoder_rsqrt_bitset_control', 'GenerateModel')">GenerateModel</a> ### Begin model generation 'gm_hdlcoder_rsqrt_bitset_control'... ### Rendering DUT with optimization related changes (IO, Area, Pipelining)... ### Model generation complete. ### Generated model saved at <a href="matlab:open_system('hdl_prj/hdlsrc/hdlcoder_rsqrt_bitset_control/gm_hdlcoder_rsqrt_bitset_control.slx')">hdl_prj/hdlsrc/hdlcoder_rsqrt_bitset_control/gm_hdlcoder_rsqrt_bitset_control.slx</a> ### Begin VHDL Code Generation for 'hdlcoder_rsqrt_bitset_control'. ### Working on... <a href="matlab:configset.internal.open('hdlcoder_rsqrt_bitset_control', 'Traceability')">Traceability</a> ### Working on hdlcoder_rsqrt_bitset_control/rSqrt/rSqrt/rSqrt_iv/NewtonPolynomialIVStage as hdl_prj/hdlsrc/hdlcoder_rsqrt_bitset_control/NewtonPolynomialIVStage.vhd. ### Working on hdlcoder_rsqrt_bitset_control/rSqrt/rSqrt/rSqrt_iv as hdl_prj/hdlsrc/hdlcoder_rsqrt_bitset_control/rSqrt_iv.vhd. ### Working on hdlcoder_rsqrt_bitset_control/rSqrt/rSqrt/rSqrt_core as hdl_prj/hdlsrc/hdlcoder_rsqrt_bitset_control/rSqrt_core.vhd. ### Working on hdlcoder_rsqrt_bitset_control/rSqrt/rSqrt as hdl_prj/hdlsrc/hdlcoder_rsqrt_bitset_control/rSqrt_block.vhd. ### Working on hdlcoder_rsqrt_bitset_control/rSqrt as hdl_prj/hdlsrc/hdlcoder_rsqrt_bitset_control/rSqrt.vhd. ### Generating package file hdl_prj/hdlsrc/hdlcoder_rsqrt_bitset_control/rSqrt_pkg.vhd. ### Code Generation for 'hdlcoder_rsqrt_bitset_control' completed. ### Generating HTML files for code generation report at <a href="matlab:hdlcoder.report.openDdg('/tmp/Bdoc24b_2679053_1581618/tp3d8bb0a0/hdlcoder-ex74485697/hdl_prj/hdlsrc/hdlcoder_rsqrt_bitset_control/html/hdlcoder_rsqrt_bitset_control_codegen_rpt.html')">hdlcoder_rsqrt_bitset_control_codegen_rpt.html</a> ### Creating HDL Code Generation Check Report file:///tmp/Bdoc24b_2679053_1581618/tp3d8bb0a0/hdlcoder-ex74485697/hdl_prj/hdlsrc/hdlcoder_rsqrt_bitset_control/rSqrt_report.html ### HDL check for 'hdlcoder_rsqrt_bitset_control' complete with 0 errors, 0 warnings, and 1 messages. ### HDL code generation complete.
rSqrt Block Synthesis Performance
This figure shows the rSqrt block synthesis performance on the Xilinx® Zynq®-7000 and Intel® Arria10® V devices.